公开(公告)号：US20240215214A1

公开(公告)日：2024-06-27

申请号：US18601094

申请日：2024-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tetsu OHTOU ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Yasutoshi OKUNO ,  Jiun-Jia HUANG

IPC: H10B10/00 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10

CPC classification number: H10B10/12 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1095 ,  H01L21/823878

Abstract: A device incudes a substrate. A first fin and a second fin are over the substrate. An isolation structure is laterally between the first fin and the second fin. A gate structure crosses the first fin and the second fin. A first source/drain epitaxy structure is over the first fin. A second source/drain epitaxy structure is over the second fin. A spacer layer extends from a first sidewall of the first fin to a first sidewall of the second fin along a top surface of the isolation structure.

公开(公告)号：US20200135902A1

公开(公告)日：2020-04-30

申请号：US16725537

申请日：2019-12-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tetsu OHTOU ,  Yusuke ONIKI

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/8234

Abstract: In a method for manufacturing a semiconductor device by using a gate replacement technology, a gate space constituted by dielectric material portions, in which a semiconductor fin channel layer is exposed, is formed. The surfaces of the dielectric material portions are made hydrophobic. A first dielectric layer is formed on the semiconductor fin channel layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A surface of the formed first dielectric layer is hydrophilic. A first conductive layer is formed over the first dielectric layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A second conductive layer is formed over the first conductive layer and on the hydrophobic surfaces of the dielectric material portions, thereby filling the gate space.

公开(公告)号：US20200020689A1

公开(公告)日：2020-01-16

申请号：US16034520

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tetsu OHTOU ,  Ching-Wei TSAI ,  Jiun-Jia HUANG ,  Kuan-Lun CHENG ,  Chi-Hsing HSU

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

公开(公告)号：US20180151494A1

公开(公告)日：2018-05-31

申请号：US15453963

申请日：2017-03-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tetsu OHTOU ,  Yusuke ONIKI ,  Hidehiro FUJIWARA

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L23/5228 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5286 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/66545

Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.

公开(公告)号：US20210013327A1

公开(公告)日：2021-01-14

申请号：US17034744

申请日：2020-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tetsu OHTOU ,  Yusuke ONIKI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/417

Abstract: In a method for manufacturing a semiconductor device by using a gate replacement technology, a gate space constituted by dielectric material portions, in which a semiconductor fin channel layer is exposed, is formed. The surfaces of the dielectric material portions are made hydrophobic. A first dielectric layer is formed on the semiconductor fin channel layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A surface of the formed first dielectric layer is hydrophilic. A first conductive layer is formed over the first dielectric layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A second conductive layer is formed over the first conductive layer and on the hydrophobic surfaces of the dielectric material portions, thereby filling the gate space.

公开(公告)号：US20220328497A1

公开(公告)日：2022-10-13

申请号：US17851675

申请日：2022-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tetsu OHTOU ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Yasutoshi OKUNO ,  Jiun-Jia HUANG

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

Abstract: A device incudes a substrate. A first fin and a second fin are over the substrate. An isolation structure is laterally between the first fin and the second fin. A gate structure crosses the first fin and the second fin. A first source/drain epitaxy structure is over the first fin. A second source/drain epitaxy structure is over the second fin. A spacer layer extends from a first sidewall of the first fin to a first sidewall of the second fin along a top surface of the isolation structure.

公开(公告)号：US20200279853A1

公开(公告)日：2020-09-03

申请号：US16876416

申请日：2020-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tetsu OHTOU ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Yasutoshi OKUNO ,  Jiun-Jia HUANG

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate; forming an shallow trench isolation (STI) structure on the substrate and between the first semiconductor fin and the second semiconductor fin; forming a spacer layer on the first semiconductor fin, the second semiconductor fin, and the STI structure; patterning the spacer layer to form a spacer extending along the second sidewall of the first semiconductor fin, a top surface of the STI structure, and the second sidewall of the second semiconductor fin; forming a first epitaxy structure in contact with a top surface of the first semiconductor fin and the first sidewall of the first semiconductor fin; and forming a second epitaxy structure in contact with a top surface of the second semiconductor fin and the first sidewall of the second semiconductor fin.

公开(公告)号：US20190139891A1

公开(公告)日：2019-05-09

申请号：US16234934

申请日：2018-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tetsu OHTOU ,  Yusuke ONIKI ,  Hidehiro FUJIWARA

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L27/11

Abstract: A method includes etching a semiconductor substrate to form a fin. An isolation structure is formed over the semiconductor substrate and around the fin. The isolation structure and the semiconductor substrate are etched to form a recess. A barrier layer is deposited over a bottom surface and a sidewall of the recess. A conductive layer is deposited over the barrier layer. The conductive layer is recessed to form a conductive line, in which a top surface of the conductive line is lower than a top surface of the isolation structure. A dielectric cap layer is formed over the conductive line. The isolation structure and the dielectric cap layer are recessed, such that the fin protrudes from the recessed isolation structure.

公开(公告)号：US20190006371A1

公开(公告)日：2019-01-03

申请号：US15905905

申请日：2018-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tetsu OHTOU ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Yasutoshi OKUNO ,  Jiun-Jia HUANG

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate having a semiconductor fin, in which the semiconductor fin has a first sidewall and a second sidewall opposite to the first sidewall; an epitaxy structure in contact with the first sidewall of the semiconductor fin; and a spacer in contact with the second sidewall of the semiconductor fin and the epitaxy structure.

公开(公告)号：US20180337266A1

公开(公告)日：2018-11-22

申请号：US16049013

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tetsu OHTOU ,  Yusuke ONIKI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/84 ,  H01L21/8238

Abstract: In a method for manufacturing a semiconductor device by using a gate replacement technology, a gate space constituted by dielectric material portions, in which a semiconductor fin channel layer is exposed, is formed. The surfaces of the dielectric material portions are made hydrophobic. A first dielectric layer is formed on the semiconductor fin channel layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A surface of the formed first dielectric layer is hydrophilic. A first conductive layer is formed over the first dielectric layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A second conductive layer is formed over the first conductive layer and on the hydrophobic surfaces of the dielectric material portions, thereby filling the gate space.