公开(公告)号：US20240379878A1

公开(公告)日：2024-11-14

申请号：US18784490

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Kuan-Lun CHENG ,  Guan-Lin CHEN ,  Kuan-Ting PAN

IPC: H01L29/786 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.

公开(公告)号：US20240274694A1

公开(公告)日：2024-08-15

申请号：US18635347

申请日：2024-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHIANG ,  Teng-Chun TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/165 ,  H01L29/7848 ,  H01L2029/7858

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.

公开(公告)号：US20240215214A1

公开(公告)日：2024-06-27

申请号：US18601094

申请日：2024-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tetsu OHTOU ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Yasutoshi OKUNO ,  Jiun-Jia HUANG

IPC: H10B10/00 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10

CPC classification number: H10B10/12 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1095 ,  H01L21/823878

Abstract: A device incudes a substrate. A first fin and a second fin are over the substrate. An isolation structure is laterally between the first fin and the second fin. A gate structure crosses the first fin and the second fin. A first source/drain epitaxy structure is over the first fin. A second source/drain epitaxy structure is over the second fin. A spacer layer extends from a first sidewall of the first fin to a first sidewall of the second fin along a top surface of the isolation structure.

公开(公告)号：US20240213313A1

公开(公告)日：2024-06-27

申请号：US18593661

申请日：2024-03-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, and a dielectric isolation plug. The semiconductor fin extends along a first direction above a substrate and includes a silicon germanium layer and a silicon layer over the silicon germanium layer. The gate structure extends across the semiconductor fin along a second direction perpendicular to the first direction. The dielectric isolation plug extends downwardly from a top surface of the silicon layer into the silicon germanium layer when viewed in a cross section taken along the first direction.

公开(公告)号：US20230246069A1

公开(公告)日：2023-08-03

申请号：US18295010

申请日：2023-04-03

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Kuo-Cheng CHING ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/0653 ,  H01L27/0886 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/4966 ,  H01L21/823871 ,  H01L29/517

Abstract: An integrated circuit (IC) structure includes a first channel region, a first gate metal engaging the first channel region, a first dielectric material layer disposed under the first gate metal and on an end of the first gate metal, a second channel region, a second gate metal engaging the second channel region, a second dielectric material layer disposed under the second gate metal and on an end of the second gate metal, and a dielectric block disposed between the end of the first gate metal and the end of the second gate metal. A horizontal portion of the first dielectric material layer abuts a horizontal portion of the second dielectric material layer, and the horizontal portion of the first dielectric material layer and the horizontal portion of the second dielectric material layer are in physical contact with the dielectric block.

公开(公告)号：US20230029370A1

公开(公告)日：2023-01-26

申请号：US17381006

申请日：2021-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin HUANG ,  Lung-Kun CHU ,  Chung-Wei HSU ,  Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A method for processing an integrated circuit includes forming N-type and P-type gate all around transistors and core gate all around transistors. The method deposits a metal gate layer for the P-type transistors. The method forms a passivation layer in-situ with the metal gate layer of the P-type transistor.

公开(公告)号：US20230009349A1

公开(公告)日：2023-01-12

申请号：US17370822

申请日：2021-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Mao-Lin HUANG ,  Lung-Kun CHU ,  Chung-Wei HSU ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/51 ,  H01L21/8234

Abstract: A method for processing an integrated circuit includes forming I/O gate all around transistors and core gate all around transistors. The method performs a regrowth process on an interfacial gate dielectric layer of the I/O gate all around transistors by diffusing metal atoms into the interfacial dielectric layer I/O gate all around transistor. The regrowth process does not diffuse metal atoms into the interfacial gate dielectric layer of the gate all around core transistor.

公开(公告)号：US20220328478A1

公开(公告)日：2022-10-13

申请号：US17481668

申请日：2021-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei JHAN ,  Kuan-Ting PAN ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/66

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate laterally offset from the first semiconductor channel. A first gate structure and a second gate structure are over and laterally surround the first and second semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure. A dielectric feature over the inactive fin includes multiple layers of dielectric material formed through alternating deposition and etching steps.

公开(公告)号：US20220320090A1

公开(公告)日：2022-10-06

申请号：US17476140

申请日：2021-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei HSU ,  Kuo-Cheng CHIANG ,  Mao-Lin HUANG ,  Lung-Kun CHU ,  Jia-Ni YU ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region and second channel nanostructures in a second device region. The first channel nanostructures are disposed between first and second dielectric fins. The second channel nanostructures are disposed between first and third dielectric fins. A gate dielectric layer is formed to surround each of the first and the second channel nanostructures and over the first, the second and the third dielectric fins. A first work function layer is formed to surround each of the first channel nanostructures. A second work function layer is formed to surround each of the second channel nanostructures. A first gap is present between every adjacent first channel nanostructures and a second gap present is between every adjacent second channel nanostructures.

公开(公告)号：US20210098625A1

公开(公告)日：2021-04-01

申请号：US16586523

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wei TSAI ,  Yu-Xuan HUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG ,  Min CAO ,  Jung-Hung CHANG ,  Lo-Heng CHANG ,  Pei-Hsun WANG ,  Kuo-Cheng CHIANG

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a substrate. The substrate has a base, a first fin structure, and a second fin structure over the base, the second fin structure is wider than the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack, and the second fin structure, which is not covered by the second gate stack. The method includes forming an inner spacer layer over the first fin structure, which is not covered by the first gate stack. The method includes forming a first stressor and a second stressor respectively over the inner spacer layer and the second fin structure, which is not covered by the second gate stack.