中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.017 seconds)

    Parasitic component library and method for efficient circuit design and simulation using the same
    2.
    发明授权
    Parasitic component library and method for efficient circuit design and simulation using the same 有权
    寄生元件库和方法用于高效电路设计和仿真使用

    公开(公告)号：US09348965B2

    公开(公告)日：2016-05-24

    申请号：US14542690

    申请日：2014-11-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Sheng Chen ,  Tsun-Yu Yang ,  Wei-Yi Hu ,  Tao Wen Chung ,  Jui-Feng Kuan ,  Yi-Kan Cheng

    IPC: G06F9/455 ,  G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5045

    Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.

    Abstract translation: 一种用于电路设计的方法包括嵌入一个或多个参数化单元的寄生感知库。 寄生感知库用于将表示电路的一些但不是全部寄生效应的网络插入到电路原理图中，使单个电路原理图用于电路仿真，电路的寄生校验和LVS（布局与原理图）检查 。 电路设计过程只需要单一电路原理图，并形成掩模组。 识别单个电路原理图的关键路径，并提取寄生效应并将其插入原理图，使得能够执行寄生验证的预估计，并使用具有一些寄生效应的电路原理图进行LVS检查， 其中包括布局的所有寄生分量的后布局模拟。

    Parasitic component library and method for efficient circuit design and simulation using the same
    4.
    发明授权
    Parasitic component library and method for efficient circuit design and simulation using the same 有权
    寄生元件库和方法用于高效电路设计和仿真使用

    公开(公告)号：US08893066B2

    公开(公告)日：2014-11-18

    申请号：US13728295

    申请日：2012-12-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Sheng Chen ,  Tsun-Yu Yang ,  Wei-Yi Hu ,  Tao Wen Chung ,  Jui-Feng Kuan ,  Yi-Kan Cheng

    IPC: G06F9/455 ,  G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5045

    Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.

    Abstract translation: 一种用于电路设计的方法包括嵌入一个或多个参数化单元的寄生感知库。 寄生感知库用于将表示电路的一些但不是全部寄生效应的网络插入到电路原理图中，使单个电路原理图用于电路仿真，电路的寄生校验和LVS（布局与原理图）检查 。 电路设计过程只需要单一电路原理图，并形成掩模组。 识别单个电路原理图的关键路径，并提取寄生效应并将其插入原理图，使得能够执行寄生验证的预估计，并使用具有一些寄生效应的电路原理图进行LVS检查， 其中包括布局的所有寄生分量的后布局模拟。

    Method for integrated circuit design
    5.
    发明授权
    Method for integrated circuit design 有权

    公开(公告)号：US12204839B2

    公开(公告)日：2025-01-21

    申请号：US17719336

    申请日：2022-04-12

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tsun-Yu Yang ,  Ren-Hong Fu ,  Chin-Cheng Kuo ,  Jui-Feng Kuan

    IPC: G06F30/30 ,  G06F30/31 ,  G06F30/3308 ,  G06F30/392

    Abstract: A method is disclosed herein. The method includes: providing, by an electronic design automation (EDA), a trigger signal to an application programming interface (API); providing, by the API, first parameters associated with parameterized cells in a netlist of an integrated circuit (IC); adjusting, by the API, the first parameters to generate second parameters associated with the parameterized cells in the netlist of the IC; updating, by the API, the netlist of the IC according to the second parameters; and performing, by the EDA, a simulation according to the netlist.

    Method of radio-frequency and microwave device generation
    6.
    发明授权
    Method of radio-frequency and microwave device generation 有权
    射频和微波器件生成方法

    公开(公告)号：US08856701B1

    公开(公告)日：2014-10-07

    申请号：US13795220

    申请日：2013-03-12

    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd

    Inventor： Chin-Sheng Chen ,  Tsun-Yu Yang ,  Wei-Yi Hu ,  Tao Wen Chung ,  Hui Yu Lee ,  Jui-Feng Kuan ,  Yi-Kan Cheng

    IPC: G06F17/50 ,  G06F9/45

    CPC classification number: G06F17/5045 ,  G06F17/5081

    Abstract: The present disclosure relates to an apparatus and method to generate a device library, along with layout versus schematic (LVS) and parasitic extraction set-up files for connecting with official tools of a design window supported by a process design kit (PDK). The device library comprises passive devices which can be utilized at any point in an end-to-end design flow from pre-layout verification to post-layout verification of an integrated circuit design. The device library allows for a single schematic view for pre-layout verification but also post-layout verification, thus allowing for pole or pin comparison, and prevents double-counting of parasitic effects from passive design elements by directly instantiating a device from the device library for a verification step. An LVS and parasitic extraction graphical user interface (GUI) allows for incorporation of the generated device library into a pre-existing PDK without any modification to the PDK. Other devices and methods are also disclosed.

    Abstract translation: 本公开涉及一种用于生成装置库的装置和方法，以及用于与由过程设计工具（PDK）支持的设计窗口的官方工具连接的布局与示意图（LVS）和寄生提取设置文件。 设备库包括无源器件，其可以在从布局前验证到集成电路设计的布局后验证的端到端设计流程中的任何点处使用。 器件库允许用于预布局验证的单个原理图，还可以进行布局后验证，从而允许极或引脚比较，并通过从器件库直接实例化器件来防止来自被动设计元件的寄生效应的双重计数 用于验证步骤。 LVS和寄生提取图形用户界面（GUI）允许将生成的设备库并入到先前存在的PDK中，而不对PDK进行任何修改。 还公开了其它装置和方法。

    METHOD OF RADIO-FREQUENCY AND MICROWAVE DEVICE GENERATION
    7.
    发明申请
    METHOD OF RADIO-FREQUENCY AND MICROWAVE DEVICE GENERATION 有权
    无线电频率和微波器件产生方法

    公开(公告)号：US20140282308A1

    公开(公告)日：2014-09-18

    申请号：US13795220

    申请日：2013-03-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Sheng Chen ,  Tsun-Yu Yang ,  Wei-Yi Hu ,  Tao Wen Chung ,  Hui Yu Lee ,  Jui-Feng Kuan ,  Yi-Kan Cheng

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  G06F17/5081

    Abstract: The present disclosure relates to an apparatus and method to generate a device library, along with layout versus schematic (LVS) and parasitic extraction set-up files for connecting with official tools of a design window supported by a process design kit (PDK). The device library comprises passive devices which can be utilized at any point in an end-to-end design flow from pre-layout verification to post-layout verification of an integrated circuit design. The device library allows for a single schematic view for pre-layout verification but also post-layout verification, thus allowing for pole or pin comparison, and prevents double-counting of parasitic effects from passive design elements by directly instantiating a device from the device library for a verification step. An LVS and parasitic extraction graphical user interface (GUI) allows for incorporation of the generated device library into a pre-existing PDK without any modification to the PDK. Other devices and methods are also disclosed.

    Abstract translation: 本公开涉及一种用于生成装置库的装置和方法，以及用于与由过程设计工具（PDK）支持的设计窗口的官方工具连接的布局与示意图（LVS）和寄生提取设置文件。 设备库包括无源器件，其可以在从布局前验证到集成电路设计的布局后验证的端到端设计流程中的任何点处使用。 器件库允许用于预布局验证的单个原理图，还可以进行布局后验证，从而允许极或引脚比较，并通过从器件库直接实例化器件来防止来自被动设计元件的寄生效应的双重计数 用于验证步骤。 LVS和寄生提取图形用户界面（GUI）允许将生成的设备库并入到先前存在的PDK中，而不对PDK进行任何修改。 还公开了其它装置和方法。

Patent Agency Ranking