公开(公告)号：US11532577B2

公开(公告)日：2022-12-20

申请号：US16989466

申请日：2020-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Ting Shih ,  Nai-Wei Liu ,  Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.

公开(公告)号：US20200373264A1

公开(公告)日：2020-11-26

申请号：US16989466

申请日：2020-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Ting Shih ,  Nai-Wei Liu ,  Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.