公开(公告)号：US20210183772A1

公开(公告)日：2021-06-17

申请号：US17164449

申请日：2021-02-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng LIN ,  Cheng-Chi CHUANG ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Hui-Ting YANG ,  Wayne LAI

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/02 ,  H01L27/088 ,  H01L27/118

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.