公开(公告)号：US20190096909A1

公开(公告)日：2019-03-28

申请号：US16022821

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Cheng-Chi CHUANG ,  Chih-Ming LAI ,  Chia-Tien WU ,  Charles Chew-Yuen YOUNG ,  Hui-Ting YANG ,  Jiann-Tyng TZENG ,  Ru-Gun LIU ,  Wei-Cheng LIN ,  Lei-Chun CHOU ,  Wei-An LAI

IPC: H01L27/118 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

公开(公告)号：US20210183772A1

公开(公告)日：2021-06-17

申请号：US17164449

申请日：2021-02-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng LIN ,  Cheng-Chi CHUANG ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Hui-Ting YANG ,  Wayne LAI

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/02 ,  H01L27/088 ,  H01L27/118

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.

公开(公告)号：US20180166431A1

公开(公告)日：2018-06-14

申请号：US15699990

申请日：2017-09-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Cheng LIN ,  Hui-Ting YANG ,  Shih-Wei PENG ,  Jiann-Tyng TZENG ,  Charles Chew-Yuen YOUNG ,  Chih-Ming LAI

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/088 ,  H01L27/0886

Abstract: A semiconductor device includes at least one first gate strip, at least one second gate strip, at least one first conductive line and at least one first conductive via. An end surface of the at least one first gate strip and an end surface of the at least one second gate strip are opposite each other. The at least one first conductive line is over the at least one first gate strip and the at least one second gate strip and across the end surface of the at least one first gate strip and the end surface of the at least one second gate strip. The at least one first conductive via connects the at least one first conductive line and the at least one first gate strip.