公开(公告)号：US12190036B2

公开(公告)日：2025-01-07

申请号：US18447170

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Pin Chou ,  Chun-Wen Wang ,  Meng Ku Chi ,  Yan-Cheng Chen ,  Jun-Xiu Liu

IPC: G06F30/367 ,  G06N5/04 ,  G06N20/00 ,  G06T7/00 ,  G06T7/70

Abstract: A semiconductor wafer defect detection system captures test images of a semiconductor wafer. The system analyzes the test images with an analysis model trained with a machine learning process. The analysis model generates simulated integrated circuit layouts based on the test images. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layouts to reference integrated circuit layouts.

公开(公告)号：US11816411B2

公开(公告)日：2023-11-14

申请号：US17103772

申请日：2020-11-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Pin Chou ,  Chun-Wen Wang ,  Meng Ku Chi ,  Yan-Cheng Chen ,  Jun-Xiu Liu

IPC: G06F30/367 ,  G06N20/00 ,  G06N5/04 ,  G06T7/70 ,  G06T7/00

CPC classification number: G06F30/367 ,  G06N5/04 ,  G06N20/00 ,  G06T7/001 ,  G06T7/70 ,  G06T2207/10061 ,  G06T2207/20081 ,  G06T2207/30148

Abstract: A semiconductor wafer defect detection system captures test images of a semiconductor wafer. The system analyzes the test images with an analysis model trained with a machine learning process. The analysis model generates simulated integrated circuit layouts based on the test images. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layouts to reference integrated circuit layouts.