公开(公告)号：US09514261B2

公开(公告)日：2016-12-06

申请号：US14609508

申请日：2015-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Heng Kai Liu ,  Hui Yu Lee ,  Ya Yun Liu ,  Yi-Ting Lin

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method comprises: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; selecting second devices to be fabricated by a second process; substituting the second devices for the first devices in the networks of the circuit design; sorting the second devices within a selected one of the networks by device area from a largest device area to a smallest device area; and assigning each second device in the selected network to be fabricated in a respective tier of a plurality of tiers of a three dimensional integrated circuit (3D IC) for which a total area of second devices previously assigned to said respective tier is the smallest, the second devices being assigned sequentially according to the sorting.

Abstract translation: 一种方法包括：接收包括由第一制造工艺制造的第一装置的网络的电路设计; 选择通过第二过程制造的第二装置; 将第二设备替换为电路设计的网络中的第一设备; 通过设备区域从最大设备区域到最小设备区域对选定的一个网络内的第二设备进行排序; 以及将要制造的所选择的网络中的每个第二设备分配在三维集成电路（3D IC）的多层的相应层中，其中先前分配给所述相应层的第二设备的总区域最小， 第二装置根据排序按顺序分配。

公开(公告)号：US08966426B1

公开(公告)日：2015-02-24

申请号：US14057059

申请日：2013-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Heng Kai Liu ,  Hui Yu Lee ,  Ya Yun Liu ,  Yi-Ting Lin

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method comprises: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; selecting second devices to be fabricated by a second process; substituting the second devices for the first devices in the networks of the circuit design; sorting the second devices within a selected one of the networks by device area from largest device area to smallest device area; and assigning each second device in the selected network to be fabricated in a respective one of a plurality of tiers of a 3D IC for which a total area of second devices previously assigned to that tier is smallest, the second devices being assigned sequentially according to the sorting.

Abstract translation: 一种方法包括：接收包括由第一制造工艺制造的第一装置的网络的电路设计; 选择通过第二过程制造的第二装置; 将第二设备替换为电路设计的网络中的第一设备; 通过设备区域从最大设备区域到最小设备区域对选定的一个网络内的第二设备进行排序; 并且将所选择的网络中的每个第二设备分配到3D IC的多层中的相应一个中，其中先前分配给该层的第二设备的总区域最小，其中第二设备根据 排序