公开(公告)号：US08966426B1

公开(公告)日：2015-02-24

申请号：US14057059

申请日：2013-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Heng Kai Liu ,  Hui Yu Lee ,  Ya Yun Liu ,  Yi-Ting Lin

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method comprises: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; selecting second devices to be fabricated by a second process; substituting the second devices for the first devices in the networks of the circuit design; sorting the second devices within a selected one of the networks by device area from largest device area to smallest device area; and assigning each second device in the selected network to be fabricated in a respective one of a plurality of tiers of a 3D IC for which a total area of second devices previously assigned to that tier is smallest, the second devices being assigned sequentially according to the sorting.

Abstract translation: 一种方法包括：接收包括由第一制造工艺制造的第一装置的网络的电路设计; 选择通过第二过程制造的第二装置; 将第二设备替换为电路设计的网络中的第一设备; 通过设备区域从最大设备区域到最小设备区域对选定的一个网络内的第二设备进行排序; 并且将所选择的网络中的每个第二设备分配到3D IC的多层中的相应一个中，其中先前分配给该层的第二设备的总区域最小，其中第二设备根据 排序

公开(公告)号：US12159904B2

公开(公告)日：2024-12-03

申请号：US17523033

申请日：2021-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Chung Chen ,  Tsung-Hsin Yu ,  Chung-Hui Chen ,  Hui-Zhong Zhuang ,  Ya Yun Liu

IPC: H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

Abstract: The present disclosure describes structure with a substrate, a first well region, a second well region, and a third well region. The first well region is in the substrate. The second well region is in the first well region and includes a first source/drain (S/D) region. The third well region is in the substrate and adjacent to the first well region. The third well region includes a second S/D region, where a spacing between the first and second S/D regions is less than about 3 μm.

公开(公告)号：US09514261B2

公开(公告)日：2016-12-06

申请号：US14609508

申请日：2015-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Heng Kai Liu ,  Hui Yu Lee ,  Ya Yun Liu ,  Yi-Ting Lin

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method comprises: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; selecting second devices to be fabricated by a second process; substituting the second devices for the first devices in the networks of the circuit design; sorting the second devices within a selected one of the networks by device area from a largest device area to a smallest device area; and assigning each second device in the selected network to be fabricated in a respective tier of a plurality of tiers of a three dimensional integrated circuit (3D IC) for which a total area of second devices previously assigned to said respective tier is the smallest, the second devices being assigned sequentially according to the sorting.

Abstract translation: 一种方法包括：接收包括由第一制造工艺制造的第一装置的网络的电路设计; 选择通过第二过程制造的第二装置; 将第二设备替换为电路设计的网络中的第一设备; 通过设备区域从最大设备区域到最小设备区域对选定的一个网络内的第二设备进行排序; 以及将要制造的所选择的网络中的每个第二设备分配在三维集成电路（3D IC）的多层的相应层中，其中先前分配给所述相应层的第二设备的总区域最小， 第二装置根据排序按顺序分配。

公开(公告)号：US20220367637A1

公开(公告)日：2022-11-17

申请号：US17523033

申请日：2021-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Chung Chen ,  Tsung-Hsin Yu ,  Chung-Hui Chen ,  Hui-Zhong Zhuang ,  Ya Yun Liu

IPC: H01L29/10 ,  H01L27/088 ,  H01L29/08 ,  H01L21/8234

Abstract: The present disclosure describes structure with a substrate, a first well region, a second well region, and a third well region. The first well region is in the substrate. The second well region is in the first well region and includes a first source/drain (S/D) region. The third well region is in the substrate and adjacent to the first well region. The third well region includes a second S/D region, where a spacing between the first and second S/D regions is less than about 3 μm.

公开(公告)号：US09335624B2

公开(公告)日：2016-05-10

申请号：US14277108

申请日：2014-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Yu Lee ,  Chi-Wen Chang ,  Chih Ming Yang ,  Ya Yun Liu ,  Yi-Kan Cheng

IPC: G06F17/50 ,  G03F1/00

CPC classification number: G03F1/00 ,  G03F1/144 ,  G03F1/70 ,  G03F7/70466 ,  G06F17/5068 ,  G06F17/5081

Abstract: A non-transitory, computer readable storage medium is encoded with computer program instructions, such that, when the computer program instructions are executed by a computer, the computer performs a method. The method generates mask assignment information for forming a plurality of patterns on a layer of an integrated circuit (IC) by multipatterning. The mask assignment information includes, for each of the plurality of patterns, a mask assignment identifying which of a plurality of masks is to be used to form that pattern, and a mask assignment lock state for that pattern. User inputs setting the mask assignment of at least one of the plurality of patterns, and its mask assignment lock state are received. A new mask assignment is generated for each of the plurality of patterns having an “unlocked” mask assignment lock state.

Abstract translation: 非暂时的计算机可读存储介质用计算机程序指令编码，使得当计算机程序指令由计算机执行时，计算机执行方法。 该方法通过多图案产生用于在集成电路（IC）的层上形成多个图案的掩模分配信息。 对于多个图案中的每一个，掩模分配信息包括识别多个掩模中哪一个要用于形成该图案的掩模分配以及该图案的掩模分配锁定状态。 用户输入设置多个图案中的至少一个的掩模分配以及其掩码分配锁定状态。 为具有“未锁定”掩码分配锁定状态的多个图案中的每一个生成新的掩模分配。