公开(公告)号：US20250062227A1

公开(公告)日：2025-02-20

申请号：US18517577

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yen Liu ,  Chao Yi Lin

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/522

Abstract: A method includes forming an integrated circuit device on a semiconductor substrate, forming a through-via penetrating through the semiconductor substrate, and forming dummy patterns surrounding the through-via. The dummy patterns include a first plurality of dummy patterns having a first pattern density, and a second plurality of dummy patterns. The first plurality of dummy patterns are between the through-via and the second plurality of dummy patterns. The second plurality of dummy patterns have a second pattern density different from the first pattern density.

公开(公告)号：US20250046655A1

公开(公告)日：2025-02-06

申请号：US18524386

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Chao Yi Lin ,  Kuo-Yen Liu ,  Chih-Hsiang Yao

IPC: H01L21/768 ,  G06F30/392 ,  H01L23/58

Abstract: A method includes finding a first plurality of through-silicon vias from a first layout of a wafer, and finding a second plurality of through-silicon vias from the first plurality of through-silicon vias. The second plurality of through-silicon vias are connected in parallel. The second plurality of through-silicon vias are merged into a large through-silicon via to generate a second layout of the wafer.