公开(公告)号：US20180151511A1

公开(公告)日：2018-05-31

申请号：US15396909

申请日：2017-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Hong Lin ,  Kuo-Yen Liu ,  Hsin-Chun Chang ,  Tzu-Li Lee ,  Yu-Ching Lee ,  Yih-Ching Wang

IPC: H01L23/00 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L21/76805 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/585 ,  H01L27/0248 ,  H01L2224/06519 ,  H01L2224/09519 ,  H01L2224/30519 ,  H01L2224/33519

Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.

公开(公告)号：US11177211B2

公开(公告)日：2021-11-16

申请号：US16811873

申请日：2020-03-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Yen Liu ,  Boo Yeh ,  Min-Chang Liang ,  Jui-Yao Lai ,  Sai-Hooi Yeong ,  Ying-Yan Chen ,  Yen-Ming Chen

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L23/52 ,  H01L21/768

Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.

公开(公告)号：US10777510B2

公开(公告)日：2020-09-15

申请号：US15396909

申请日：2017-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Hong Lin ,  Kuo-Yen Liu ,  Hsin-Chun Chang ,  Tzu-Li Lee ,  Yu-Ching Lee ,  Yih-Ching Wang

IPC: H01L23/00 ,  H01L23/58 ,  H01L27/02 ,  H01L23/522 ,  H01L21/768

Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.

公开(公告)号：US10269697B2

公开(公告)日：2019-04-23

申请号：US15061627

申请日：2016-03-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Yen Liu ,  Boo Yeh ,  Min-Chang Liang ,  Jui-Yao Lai ,  Sai-Hooi Yeong ,  Ying-Yan Chen ,  Yen-Ming Chen

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.

公开(公告)号：US11955441B2

公开(公告)日：2024-04-09

申请号：US17706039

申请日：2022-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Hong Lin ,  Kuo-Yen Liu ,  Hsin-Chun Chang ,  Tzu-Li Lee ,  Yu-Ching Lee ,  Yih-Ching Wang

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/58 ,  H01L27/02 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/585 ,  H01L27/0248 ,  H01L21/76805 ,  H01L2224/06519 ,  H01L2224/09519 ,  H01L2224/30519 ,  H01L2224/33519

Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.

公开(公告)号：US11302654B2

公开(公告)日：2022-04-12

申请号：US17018381

申请日：2020-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Hong Lin ,  Kuo-Yen Liu ,  Hsin-Chun Chang ,  Tzu-Li Lee ,  Yu-Ching Lee ,  Yih-Ching Wang

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/58 ,  H01L27/02 ,  H01L23/522

Abstract: A method includes depositing a first dielectric layer over a substrate; forming a first dummy metal layer over the first dielectric layer, wherein the first dummy metal layer has first and second portions laterally separated from each other; depositing a second dielectric layer over the first dummy metal layer; etching an opening having an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first dummy metal layer, and a lower portion in the first dielectric layer, wherein a width of the lower portion of the opening is greater than a width of the middle portion of the opening, and a bottom of the opening is higher than a bottom of the first dielectric layer; and forming a dummy via in the opening and a second dummy metal layer over the dummy via and the second dielectric layer.

公开(公告)号：US10157826B2

公开(公告)日：2018-12-18

申请号：US15061627

申请日：2016-03-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Yen Liu ,  Boo Yeh ,  Min-Chang Liang ,  Jui-Yao Lai ,  Sai-Hooi Yeong ,  Ying-Yan Chen ,  Yen-Ming Chen

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.

公开(公告)号：US20250062227A1

公开(公告)日：2025-02-20

申请号：US18517577

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yen Liu ,  Chao Yi Lin

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/522

Abstract: A method includes forming an integrated circuit device on a semiconductor substrate, forming a through-via penetrating through the semiconductor substrate, and forming dummy patterns surrounding the through-via. The dummy patterns include a first plurality of dummy patterns having a first pattern density, and a second plurality of dummy patterns. The first plurality of dummy patterns are between the through-via and the second plurality of dummy patterns. The second plurality of dummy patterns have a second pattern density different from the first pattern density.

公开(公告)号：US20250046655A1

公开(公告)日：2025-02-06

申请号：US18524386

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Chao Yi Lin ,  Kuo-Yen Liu ,  Chih-Hsiang Yao

IPC: H01L21/768 ,  G06F30/392 ,  H01L23/58

Abstract: A method includes finding a first plurality of through-silicon vias from a first layout of a wafer, and finding a second plurality of through-silicon vias from the first plurality of through-silicon vias. The second plurality of through-silicon vias are connected in parallel. The second plurality of through-silicon vias are merged into a large through-silicon via to generate a second layout of the wafer.