公开(公告)号：US20230223076A1

公开(公告)日：2023-07-13

申请号：US18188523

申请日：2023-03-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sanjeev Kumar Jain ,  Ruchin Jain ,  Arun Achyuthan ,  Atul Katoch

IPC分类号： G11C7/12 ,  G11C7/10

CPC分类号： G11C7/12 ,  G11C7/1093

摘要： Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

公开(公告)号：US20240242762A1

公开(公告)日：2024-07-18

申请号：US18585184

申请日：2024-02-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sanjeev Kumar Jain ,  Ruchin Jain ,  Arun Achyuthan ,  Atul Katoch

IPC分类号： G11C11/419 ,  G11C7/10 ,  G11C7/12

CPC分类号： G11C11/419 ,  G11C7/1093 ,  G11C7/12 ,  G11C2207/12

摘要： Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

公开(公告)号：US11935589B2

公开(公告)日：2024-03-19

申请号：US18188523

申请日：2023-03-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sanjeev Kumar Jain ,  Ruchin Jain ,  Arun Achyuthan ,  Atul Katoch

IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C7/12 ,  G11C11/419

CPC分类号： G11C11/419 ,  G11C7/1093 ,  G11C7/12 ,  G11C2207/12

摘要： Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

公开(公告)号：US11626158B2

公开(公告)日：2023-04-11

申请号：US17246822

申请日：2021-05-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sanjeev Kumar Jain ,  Ruchin Jain ,  Arun Achyuthan ,  Atul Katoch

IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C7/12

摘要： Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

公开(公告)号：US20220130455A1

公开(公告)日：2022-04-28

申请号：US17246822

申请日：2021-05-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sanjeev Kumar Jain ,  Ruchin Jain ,  Arun Achyuthan ,  Atul Katoch

IPC分类号： G11C11/419 ,  G11C7/12

摘要： Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.