公开(公告)号：US20230037867A1

公开(公告)日：2023-02-09

申请号：US17395779

申请日：2021-08-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Han Yang ,  Lung-Hui Chen ,  Kuan-Yu Chen ,  Shih J. Wei

IPC分类号： H01L29/94 ,  H01L23/522 ,  H01L49/02

摘要： A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.

公开(公告)号：US11855230B2

公开(公告)日：2023-12-26

申请号：US17395779

申请日：2021-08-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Han Yang ,  Lung-Hui Chen ,  Kuan-Yu Chen ,  Shih J. Wei

IPC分类号： H01L29/94 ,  H01L23/522 ,  H01L49/02

CPC分类号： H01L29/94 ,  H01L23/5223 ,  H01L23/5226 ,  H01L28/56 ,  H01L28/91 ,  H01L28/92

摘要： A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.