-
公开(公告)号：US20230016849A1
公开(公告)日：2023-01-19
申请号：US17377620
申请日：2021-07-16
发明人： Ya-Huei LEE , Shu-Shen YEH , Kuo-Ching HSU , Shyue-Ter LEU , Po-Yao LIN , Shin-Puu JENG
IPC分类号： H01L23/498
摘要： A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate disposed below the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment. The first and second line segments are connected together, and the second line segment has a smaller line width than the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.
-
公开(公告)号：US20220384391A1
公开(公告)日：2022-12-01
申请号：US17818432
申请日：2022-08-09
发明人： Shu-Shen YEH , Po-Yao LIN , Shin-Puu JENG , Po-Chen LAI , Kuang-Chun LEE , Che-Chia YANG , Chin-Hua WANG , Yi Hang LIN
IPC分类号： H01L25/065 , H01L23/31 , H01L23/498 , H01L23/00 , H01L25/00
摘要： A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure and a second chip structure over the wiring substrate. The first chip structure is spaced apart from the second chip structure by a gap. The chip package structure includes a ring structure over the wiring substrate. The ring structure has a first opening, the first chip structure and the second chip structure are in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.
-
公开(公告)号：US20220384390A1
公开(公告)日：2022-12-01
申请号：US17817705
申请日：2022-08-05
发明人： Che-Chia YANG , Shu-Shen YEH , Po-Chen LAI , Ming-Chih YEW , Po-Yao LIN , Shin-Puu JENG
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00 , H01L23/31
摘要： A semiconductor device package is provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first and second package components are disposed over and bonded to the substrate. The first and second package components are different types of electronic components that provide different functions. The dummy die is disposed over and attached to the substrate. The dummy die is located between the first and second package components and is electrically isolated from the substrate.
-
公开(公告)号：US20220367314A1
公开(公告)日：2022-11-17
申请号：US17318163
申请日：2021-05-12
发明人： Shu-Shen YEH , Che-Chia YANG , Chia-Kuei HSU , Ming-Chih YEW , Po-Yao LIN , Shin-Puu JENG
IPC分类号： H01L23/373 , H01L23/29 , H01L23/58
摘要： A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, an interposer substrate over the package substrate, semiconductor dies over the interposer substrate, and an underfill element over the interposer substrate and between the semiconductor dies and interposer substrate. The semiconductor die package also includes a ring structure and one or more lid structures separated from the ring structure. The ring structure is coupled to the package substrate to control warpage. The lid structures are coupled to the top surfaces of the semiconductor dies to control warpage and help heat dissipation. In addition, the lid structures define a gap to allow a portion of the underfill element between the adjacent semiconductor dies to be exposed, so that stress concentration on that portion can be avoided or reduced. Accordingly, the reliability of the semiconductor die package is improved.
-
公开(公告)号：US20230069717A1
公开(公告)日：2023-03-02
申请号：US17459347
申请日：2021-08-27
发明人： Shu-Shen YEH , Che-Chia YANG , Yu-Sheng LIN , Chin-Hua WANG , Po-Yao LIN , Shin-Puu JENG
IPC分类号： H01L23/367 , H01L25/065 , H01L25/18 , H01L25/00 , H01L21/48
摘要： A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure over the wiring substrate. The chip package structure includes a heat-spreading lid over the wiring substrate and covering the first chip structure. The heat-spreading lid includes a ring structure and a top plate. The ring structure surrounds the first chip structure. The top plate covers the ring structure and the first chip structure. The first chip structure has a first sidewall and a second sidewall opposite to the first sidewall, a first distance between the first sidewall and the ring structure is less than a second distance between the second sidewall and the ring structure, the top plate has a first opening, the first opening has a first inner wall and a second inner wall facing each other.
-
6.发明申请公开(公告)号：US20230069311A1
公开(公告)日：2023-03-02
申请号：US17459314
申请日：2021-08-27
发明人： Shu-Shen YEH , Po-Chen LAI , Che-Chia YANG , Li-Ling LIAO , Po-Yao LIN , Shin-Puu JENG
IPC分类号： H01L25/065 , H01L23/31 , H01L23/498 , H01L21/78 , H01L21/56 , H01L21/48
摘要： A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate. The chip structure has an inclined sidewall, the inclined sidewall is at an acute angle to a vertical, the vertical is a direction perpendicular to a main surface of the chip structure, and the acute angle is in a range from about 12 degrees to about 45 degrees. The method also includes forming a protective layer to surround the chip structure.
-
公开(公告)号：US20230064957A1
公开(公告)日：2023-03-02
申请号：US17459215
申请日：2021-08-27
发明人： Yu-Sheng LIN , Shin-Puu JENG , Po-Yao LIN , Chin-Hua WANG , Shu-Shen YEH , Che-Chia YANG
IPC分类号： H01L23/538 , H01L23/13 , H01L21/683 , H01L21/48
摘要： A package structure and a formation method of a package structure are provided. The method includes forming a recess in a circuit substrate, and the recess has a first sidewall and a second sidewall. The second sidewall is between the first sidewall and a bottommost surface of the circuit substrate, and the second sidewall is steeper than the first sidewall. The method also includes forming a die package, and the die package has a semiconductor die. The method further includes bonding the die package to the circuit substrate through bonding structures such that a portion of the semiconductor die enters the recess of the circuit substrate. In addition, the method includes forming an underfill material to surround the bonding structures and to fill the recess.
-
公开(公告)号：US20230061269A1
公开(公告)日：2023-03-02
申请号：US17460705
申请日：2021-08-30
发明人： Chin-Hua WANG , Shu-Shen YEH , Po-Chen LAI , Po-Yao LIN , Shin-Puu JENG
摘要： A package structure is provided. The package structure includes a first package component and a second package component. The second package component includes a substrate and an electronic component disposed on the substrate, and the first package component is mounted to the substrate. The package structure further includes a ring structure disposed on the second package component and around the first package component. The ring structure has a first foot and a second foot, the first foot and the second foot extend toward the substrate, the electronic component is covered by the ring structure and located between the first foot and the second foot, and the first package component is exposed from the ring structure.
-
公开(公告)号：US20220359465A1
公开(公告)日：2022-11-10
申请号：US17395946
申请日：2021-08-06
发明人： Chin-Hua WANG , Shu-Shen YEH , Yu-Sheng LIN , Po-Yao LIN , Shin-Puu JENG
IPC分类号： H01L25/065 , H01L23/00 , H01L21/48
摘要： A package structure is provided. The package structure includes a first package component, a second package component, and a lid structure. The first package component includes a plurality of integrated circuit dies and an underfill formed between the integrated circuit dies. The second package component includes a substrate, and the first package component is mounted on the substrate. The lid structure is disposed on the second package component and around the first package component, and the lid structure covers the integrated circuit dies and exposes the underfill.
-
公开(公告)号：US20230100127A1
公开(公告)日：2023-03-30
申请号：US18061501
申请日：2022-12-05
发明人： Yu-Sheng LIN , Po-Yao LIN , Shu-Shen YEH , Chin-Hua WANG , Shin-Puu JENG
IPC分类号： H01L23/367 , H01L23/373 , H01L23/31 , H01L21/48
摘要： A semiconductor die package is provided. The semiconductor die package includes a package substrate, and a first semiconductor die and a second semiconductor die disposed thereon. A ring structure is attached to the package substrate and surrounds the semiconductor dies. A lid structure is attached to the ring structure and disposed over the semiconductor dies, and has an opening exposing the second semiconductor die. A heat sink is disposed over the lid structure and has a portion extending into the opening of the lid structure. A first thermal interface material (TIM) layer is interposed between the lid structure and the first semiconductor die. A second TIM layer is interposed between the extending portion of the heat sink and the second semiconductor die. The first TIM layer has a thermal conductivity higher than the thermal conductivity of the second TIM layer.
-
-
-
-
-
-
-
-
-
搜索结果
25 条记录 (耗时 0.02 秒)
