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公开(公告)号：US12230764B2
公开(公告)日：2025-02-18
申请号：US16899539
申请日：2020-06-11
Applicant: TAIYO YUDEN CO., LTD.
Inventor： Sachie Tomizawa , Daigo Ito , Chie Kawamura , Kotaro Mizuno
IPC: H01M10/0562 , H01M4/62 , H01M10/0585
Abstract: An all solid battery includes: a solid electrolyte layer of which a main component is oxide-based solid electrolyte; a first electrode layer that is provided on a first main face of the solid electrolyte layer and includes an active material; and a second electrode layer that is provided on a second main face of the solid electrolyte layer and includes an active material, wherein at least one of the first electrode layer and the second electrode layer includes an aggregate of carbon particles and a cavity, wherein the aggregate demarcates at least a part of the cavity.
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公开(公告)号：US11756737B2
公开(公告)日：2023-09-12
申请号：US17589344
申请日：2022-01-31
Applicant: TAIYO YUDEN CO., LTD.
Inventor： Kotaro Mizuno
CPC classification number: H01G4/30 , H01G4/012 , H01G4/1227
Abstract: A multi-layer ceramic capacitor includes: a multi-layer unit including ceramic layers laminated in a first direction and electrodes disposed between the ceramic layers, positions of end portions of the electrodes falling within a range of 0.5 μm in a second direction; and side margins each containing manganese or magnesium and silicon and facing each other in the second direction. When each margin is equally divided into an inner region and an outer region, a total concentration of manganese and magnesium in the outer region is higher than a total concentration of manganese and magnesium in the inner region and higher than a total concentration of manganese and magnesium in the ceramic layers, and a concentration of silicon in the inner region is not less than a concentration of silicon in the outer region and higher than a concentration of silicon in the ceramic layers.
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公开(公告)号：US11594764B2
公开(公告)日：2023-02-28
申请号：US16952998
申请日：2020-11-19
Applicant: TAIYO YUDEN CO., LTD.
Inventor： Chie Kawamura , Kotaro Mizuno
IPC: H01M10/0585 , H01M10/0525 , H01M10/0562 , H01M4/64
Abstract: An all solid battery includes a solid electrolyte layer, a first electrode structure that has a structure in which a first electric collector layer of which a main component is a conductive material is sandwiched by two first electrode layers including an active material, and a second electrode structure that has a structure in which a second electric collector layer of which a main component is a conductive material is sandwiched by two second electrode layers including an active material. Roughness of interfaces between the first electric collector layer and the two first electrode layers and/or roughness of interfaces between the second electric collector layer and the two second electrode layers is larger than roughness of interfaces between the solid electrolyte layer, and the first electrode layer and the second electrode layer sandwiching the solid electrolyte layer.
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4.发明授权公开(公告)号：US11557432B2
公开(公告)日：2023-01-17
申请号：US16852321
申请日：2020-04-17
Applicant: TAIYO YUDEN CO., LTD.
Inventor： Takehiro Tanaka , Kotaro Mizuno , Yusuke Kowase
Abstract: A ceramic electronic device includes: a multilayer chip having a structure in which each of dielectric layers and each of internal electrode layers are alternately stacked; and external electrodes provided on end faces of the multilayer chip, wherein a main component of the external electrodes is a first metal, wherein the internal electrode layers include the first metal and a second metal of which a melting point is higher than that of the first metal, wherein a diffusion coefficient of the first metal with respect to the second metal is larger than that of the second metal with respect to the first metal, wherein a number of a cavity in a range of 10 numbers of the internal electrode layers that are next to each other and are connected to a same external electrode of the first external electrode and the second external electrode is 1 or less.
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公开(公告)号：US11004607B2
公开(公告)日：2021-05-11
申请号：US15903712
申请日：2018-02-23
Applicant: TAIYO YUDEN CO., LTD.
Inventor： Shohei Kitamura , Yukihiro Konishi , Kotaro Mizuno , Yoichi Kato , Yusuke Kowase , Toru Makino , Yoshinori Tanaka
Abstract: A method for manufacturing a multilayer ceramic capacitor includes: producing a plurality of dielectric green sheets; producing therefrom a plurality of internal electrode-printed green sheets; producing therefrom a plurality of individually cut unsintered laminates by stacking some of the plurality of dielectric green sheets, as cover layers, and the plurality of internal electrode-printed green sheets together; producing therefrom element body precursors by applying a ceramic paste to side faces of the unsintered laminates for forming side margins thereon, wherein an application thickness of the ceramic paste is adjusted in a manner such that a thickness of the side margins is greater than a thickness of the cover layers in the final product; producing therefrom element bodies by sintering; and forming external electrodes on at least one of principal faces and on both end faces of the element bodies.
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Patent Agency Ranking
公开(公告)号：US10535470B2
公开(公告)日：2020-01-14
申请号：US16426874
申请日：2019-05-30
Applicant: TAIYO YUDEN CO., LTD.
Inventor： Kotaro Mizuno
Abstract: A multi-layer ceramic capacitor includes a multi-layer unit and a side margin. The multi-layer unit includes a capacitance forming unit and a cover. The capacitance forming unit includes ceramic layers laminated in a first direction and internal electrodes disposed between the ceramic layers and mainly containing nickel. The cover covers the capacitance forming unit from the first direction. The side margin covers the multi-layer unit from a second direction orthogonal to the first direction. The internal electrodes each include an oxidized area adjacent to the side margin and intensively including a metal element that forms an oxide together with nickel. The capacitance forming unit includes a first portion adjacent to the cover and a second portion adjacent to the first portion in the first direction and including the oxidized area having a smaller dimension in the second direction than that of the oxidized area of the first portion.
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公开(公告)号：US10475579B2
公开(公告)日：2019-11-12
申请号：US15909516
申请日：2018-03-01
Applicant: Taiyo Yuden Co., Ltd.
Inventor： Daisuke Sakate , Kotaro Mizuno
Abstract: A multi-layer ceramic capacitor includes a multi-layer unit and a side margin. The multi-layer unit includes ceramic layers laminated in a first direction, and internal electrodes disposed between the ceramic layers. The side margin covers the multi-layer unit from a second direction orthogonal to the first direction, the side margin having a higher concentration of a rare-earth element and a higher concentration of vanadium than center portions of the ceramic layers in the second direction.
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公开(公告)号：US10262800B2
公开(公告)日：2019-04-16
申请号：US15461255
申请日：2017-03-16
Applicant: TAIYO YUDEN CO., LTD.
Inventor： Kotaro Mizuno , Yoichi Kato
Abstract: In an embodiment, one length-direction end of each first internal electrode layer 111a of the capacitor body 110 is connected, via the conductive part 114a of the first relay layer 114 connected over a connection width equivalent to the width of each first internal electrode layer 111a, to the first external electrode 120 provided on one height-direction face of the capacitor body 110; also, the other length-direction end of each second internal electrode layer 111b is connected, via the conductive part 115a of the second relay layer 115 connected over a connection width equivalent to the width of each second internal electrode layer 111b, to the second external electrode 130 provided on one height-direction face of the capacitor body 110.
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公开(公告)号：US12260995B2
公开(公告)日：2025-03-25
申请号：US18649416
申请日：2024-04-29
Applicant: TAIYO YUDEN CO., LTD.
Inventor： Kotaro Mizuno
Abstract: A ceramic electronic device includes a multilayer chip in which dielectric layers and internal electrode layers each including Ni as a main phase are alternately stacked. At least one of the dielectric layers includes Si. One of the internal electrode layers next to the at least one of the dielectric layers includes a layer including an additive element including one or more of Au, Pt, Cu, Fe, Cr, Zn, and In. A peak of a concentration of the additive element and/or a peak of a concentration of Si in the one of the internal electrode layers and the at least one of the dielectric layers exist(s) in a region within 15 nm in a thickness direction from an interface between the one of the internal electrode layers and the at least one of the dielectric layers.
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公开(公告)号：US11948753B2
公开(公告)日：2024-04-02
申请号：US18327805
申请日：2023-06-01
Applicant: TAIYO YUDEN CO., LTD.
Inventor： Kazuki Yamada , Kotaro Mizuno , Yoichi Kato , Hidetoshi Masuda
IPC: H01G4/30 , C04B35/468 , H01G4/008 , H01G4/012 , H01G4/12
CPC classification number: H01G4/30 , C04B35/4682 , H01G4/008 , H01G4/012 , H01G4/1218 , C04B2235/65
Abstract: A manufacturing method of a multilayer ceramic electronic device includes: forming each of stack units by forming each of internal electrode patterns on each of dielectric green sheets, the each of internal electrode patterns including Ni, Sn and Au; forming a multilayer structure by stacking the each of stack units; and firing the multilayer structure, whereby each internal electrode layer is formed from the each of internal electrode patterns and each dielectric layer is formed from the each of the dielectric green sheets wherein, in the each internal electrode layer, an Au concentration near each interface between the each internal electrode layer and the each dielectric layer is larger than an Au concentration in each center portion in a thickness direction.
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