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公开(公告)号：US06549198B1
公开(公告)日：2003-04-15
申请号：US09456816
申请日：1999-12-08
IPC分类号： G09G500
CPC分类号： G09G1/167 , G09G2340/0478 , H04N5/126 , H04N5/46
摘要： Disclosed is a HOUT position control circuit used to control the horizontal position of display image in a multisync monitor. The circuit has: a first PLL circuit that is phase-locked with input horizontal synchronous signal; a second PLL circuit that is phase-locked with output of the first PLL circuit; and a circuit for generating a delay between outputs of the first PLL circuit and the second PLL circuit to control the delay amount from the input horizontal synchronous signal to output horizontal drive signal.
摘要翻译： 公开了用于控制多同步监视器中的显示图像的水平位置的HOUT位置控制电路。 该电路具有：与输入水平同步信号锁相的第一个PLL电路; 与所述第一PLL电路的输出锁相的第二PLL电路; 以及用于在第一PLL电路和第二PLL电路的输出之间产生延迟以控制从输入水平同步信号到输出水平驱动信号的延迟量的电路。
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2.发明授权Lock-in detecting circuit having variable window for checking phase locked loop and method used therein 失效具有用于检查锁相环的可变窗口的锁定检测电路及其中使用的方法公开(公告)号：US06222400B1
公开(公告)日：2001-04-24
申请号：US09472950
申请日：1999-12-27
IPC分类号： H03L700
摘要： A phase locked loop makes a system clock signal synchronous to a horizontal synchronizing signal for a display unit, and a lock-in detecting circuit monitors said phase locked loop to see whether or not a phase difference takes place between the system clock signal and the horizontal synchronizing signal, wherein the lock-in detecting circuit measures the unlocked state between the system clock signal and the horizontal synchronizing signal in a window defined in a vertical synchronizing period and, thereafter, compares the time period of the unlocked state with a critical value to see whether or not the unlocked state is due to a temporary phenomenon or a phase difference to be corrected so that an detecting signal of the lock-in detecting circuit is reliable.
摘要翻译： 锁相环使系统时钟信号与用于显示单元的水平同步信号同步，并且锁定检测电路监视所述锁相环，以查看在系统时钟信号和水平面之间是否发生相位差 同步信号，其中所述锁定检测电路在垂直同步周期中定义的窗口中测量所述系统时钟信号和所述水平同步信号之间的解锁状态，然后将所述解锁状态的时间周期与临界值进行比较 查看解锁状态是否由于临时现象或相位差被校正，使得锁定检测电路的检测信号是可靠的。
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3.发明授权Deflection correction circuit for narrowing a pull-in range of a VCO to reduce frequency variations in a horizontal synchronizing signal 失效用于缩小VCO的拉入范围以减小水平同步信号中的频率变化的偏转校正电路公开(公告)号：US06486857B1
公开(公告)日：2002-11-26
申请号：US09503177
申请日：2000-02-14
IPC分类号： G09G108
摘要： There is disclosed a phase-locked loop (PLL) circuit for use in an improved deflection correction circuit for a larger and flat display device. The PLL circuit has a phase comparator circuit, a filter, and a voltage-controlled oscillator (VCO) connected in series in this order. The output signal from the VCO is fed back to the phase comparator circuit. The PLL circuit further includes a period-detecting circuit for detecting the period of an externally applied signal and a frequency divider circuit. This frequency divider circuit divides the frequency of the output signal from the VCO according to the period detected by the period-detecting circuit and feeds the resulting signal back to the VCO.
摘要翻译： 公开了一种用于更大和平坦的显示装置的改进的偏转校正电路中的锁相环（PLL）电路。 PLL电路具有按顺序串联连接的相位比较器电路，滤波器和压控振荡器（VCO）。 来自VCO的输出信号被反馈到相位比较器电路。 PLL电路还包括用于检测外部施加的信号的周期的周期检测电路和分频器电路。 该分频器电路根据由周期检测电路检测到的周期来分频来自VCO的输出信号的频率，并将所得到的信号反馈给VCO。
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公开(公告)号：US06573798B2
公开(公告)日：2003-06-03
申请号：US09901726
申请日：2001-07-11
申请人： Yoshiyuki Uto
发明人： Yoshiyuki Uto
IPC分类号： H03L700
CPC分类号： H03L7/0898 , H03L7/18 , H03L2207/04
摘要： A PLL system includes a phase comparator, charge pump, LPF, VCO, 1/N frequency divider, CRT drive circuit, and arithmetic unit. The charge pump outputs a charge pump signal in accordance with the phase error signal output from the phase comparator. The current capacity of the charge pump is controlled to keep a PLL loop gain constant by compensation for a variation in PLL loop gain due to a change in a frequency division ratio 1/N in the frequency divider.
摘要翻译： PLL系统包括相位比较器，电荷泵，LPF，VCO，1 / N分频器，CRT驱动电路和算术单元。 电荷泵根据从相位比较器输出的相位误差信号输出电荷泵信号。 通过对分频器中分频比1 / N的变化引起的PLL环路增益的变化进行补偿来控制电荷泵的电流容量，以保持PLL环路增益恒定。
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