公开(公告)号：US20130236939A1

公开(公告)日：2013-09-12

申请号：US13878469

申请日：2011-10-21

Applicant: Yutaka Nakai ,  Yasunori Baba ,  Chika Tada ,  Yasuhiro Fukuda

Inventor： Yutaka Nakai ,  Yasunori Baba ,  Chika Tada ,  Yasuhiro Fukuda

IPC: C12P7/54 ,  C12P5/02

CPC classification number: C12P7/54 ,  C02F3/00 ,  C12N1/22 ,  C12P5/023 ,  C12P7/52 ,  C12P2203/00 ,  D21C5/02 ,  Y02E50/343 ,  Y02W30/648

Abstract: The present application provides a method for producing organic acid, such as acetic acid, propionic acid, butyric acid, or another high-quality raw material designed for methane fermentation and obtained by converting waste paper and other forms of cellulose-based biomass to organic acid, wherein said method comprising a step for reacting rumen fluid collected from a ruminant animal with cellulose-containing waste matter. This method provides the effective use of cellulose-containing waste matter, which is a high-quality fermentation resource.

Abstract translation: 本申请提供了一种生产有机酸的方法，例如乙酸，丙酸，丁酸，或另一种设计用于甲烷发酵的优质原料，通过将废纸和其它形式的纤维素基生物质转化为有机酸获得 其中所述方法包括使从反刍动物收集的瘤胃液与含纤维素的废物反应的步骤。 这种方法提供了有效利用含有纤维素的废物，这是一种高品质的发酵资源。

公开(公告)号：US20120076897A1

公开(公告)日：2012-03-29

申请号：US13260117

申请日：2010-03-24

Applicant: Tsuyoshi Goto ,  Yasuhiro Fukuda ,  Itaru Shioya ,  Hideki Nikaido ,  Yosuke Tanaka ,  Taeko Kousaka

Inventor： Tsuyoshi Goto ,  Yasuhiro Fukuda ,  Itaru Shioya ,  Hideki Nikaido ,  Yosuke Tanaka ,  Taeko Kousaka

IPC: A23K1/18 ,  A23K1/16

CPC classification number: A23K50/80 ,  A23K20/158 ,  A23K40/30 ,  Y02A40/818

Abstract: [Problem]To provide a feed for fish farming which is excellent in terms of stability of feed supply and feed shelf life and which has excellent feed intake and feed efficiency.[Solution]A feed for fish farming consisting of an outer layer and an inner layer, characterized in that a composition constituting the outer layer has a breaking stress of 5×104 to 1×106 N/m2, a cohesiveness (30%) of 0.4 to 1.0, and a breaking strain of 30 to 80%. A feed for fish farming characterized by consisting of an outer layer constructed from a heat-induced gel which comprises a protein and/or a starch, and an inner layer comprising a composition which contains nutrient ingredients having fish meal and an oil as essential ingredients. As the protein, surimi, ground fish meat, krill, gelatin, collagen, gluten, egg albumen and soy bean protein are preferred. As the starch, tapioca starch, wheat starch, potato starch, corn starch, bean starch, waxy corn starch and processed products of these starches are preferred.

Abstract translation: [问题]提供饲料供应稳定性和饲料保质期优异的鱼饲料，并且具有优异的进料量和进料效率。 [解决方案]一种由外层和内层构成的鱼饲料，其特征在于，构成外层的组合物的断裂应力为5×10 4〜1×10 6 N / m 2，内聚力（30％）为 0.4〜1.0，断裂应变为30〜80％。 一种用于鱼类养殖的饲料，其特征在于由包含蛋白质和/或淀粉的热诱导凝胶构成的外层，以及包含含有具有鱼粉和油作为必需成分的营养成分的组合物的内层。 作为蛋白质，优选鱼糜，地面鱼肉，磷虾，明胶，胶原蛋白，麸质，蛋清蛋白和大豆蛋白。 作为淀粉，木薯淀粉，小麦淀粉，马铃薯淀粉，玉米淀粉，豆淀粉，蜡质玉米淀粉和这些淀粉的加工产物是优选的。

公开(公告)号：US20090079028A1

公开(公告)日：2009-03-26

申请号：US12292032

申请日：2008-11-10

Applicant: Yasuhiro Fukuda

Inventor： Yasuhiro Fukuda

IPC: H01L23/525

CPC classification number: H01L23/5258 ,  H01L27/0288 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device has a fuse, an internal circuit and a protection capacitor. The fuse has a first terminal connected to be applied to a fixed voltage and a second terminal. The internal circuit includes a transistor. The transistor has a threshold voltage and a gate. The protection capacitor is connected between the second terminal of the fuse and the gate of the transistor. The protection capacitor supplies the threshold voltage to the transistor where the fuse supplies the fixed voltage to the protection capacitor.

Abstract translation: 半导体器件具有熔丝，内部电路和保护电容器。 保险丝具有连接到固定电压的第一端子和第二端子。 内部电路包括晶体管。 晶体管具有阈值电压和栅极。 保护电容器连接在熔丝的第二端和晶体管的栅极之间。 保护电容器将阈值电压提供给晶体管，其中保险丝将固定电压提供给保护电容。

公开(公告)号：US20070018446A1

公开(公告)日：2007-01-25

申请号：US10569740

申请日：2004-08-30

Applicant: Yukihiko Isetani ,  Takaaki Okada ,  Hideo Shimizu ,  Yoshiaki Ide ,  Yasuhiro Fukuda ,  Takeshi Yamakami ,  Fumihiro Hanazawa ,  Akira Yamazaki

Inventor： Yukihiko Isetani ,  Takaaki Okada ,  Hideo Shimizu ,  Yoshiaki Ide ,  Yasuhiro Fukuda ,  Takeshi Yamakami ,  Fumihiro Hanazawa ,  Akira Yamazaki

IPC: H04M1/64 ,  B42D15/00

CPC classification number: H01M2/10 ,  B42D15/022 ,  H01M6/40

Abstract: Sheet-like audio information recording/reproducing means capable of recording/reproducing audio information is sandwiched between two support sheets from front and back only in part of the area thereof and these two support sheets are further sandwiched between two surface sheets and the support sheets and surface sheets are bonded together.

Abstract translation: 能够记录/再现音频信息的片状音频信息记录/再现装置夹在两个支撑片之间的前后仅在其一部分区域中，并且这两个支撑片进一步夹在两个表面片和支撑片之间， 表面片材结合在一起。

公开(公告)号：US20060220137A1

公开(公告)日：2006-10-05

申请号：US11276823

申请日：2006-03-15

Applicant: Toshikazu KURODA ,  Hirokazu HAYASHI ,  Yasuhiro FUKUDA

Inventor： Toshikazu KURODA ,  Hirokazu HAYASHI ,  Yasuhiro FUKUDA

IPC: H01L29/74

CPC classification number: H01L27/0262

Abstract: An electro-static discharge protection circuit and a semiconductor device having the same is disclosed. The electro-static discharge protection circuit has a current control circuit. The current control circuit has a first capacitive element. When the external source voltage is applied to the external source voltage supply line, the booster circuit in the internal circuitry boosts the internal source voltage of the internal source voltage supply line. The external source voltage becomes transiently greater than the internal source voltage at the early stage of the boosting step when the booster circuit boosts the internal source voltage based on the external source voltage. The first capacitive element restricts a current from flowing from the second terminal of the thyristor rectifier circuit to the internal source voltage, even when the external source voltage becomes transiently greater than the internal source voltage at the early stage of the boosting step when the booster circuit boosts the internal source voltage based on the external source voltage. This prevents the thyristor rectifier circuit from malfunctioning and turning on.

Abstract translation: 公开了一种静电放电保护电路及具有该静电放电保护电路的半导体器件。 静电放电保护电路具有电流控制电路。 电流控制电路具有第一电容元件。 当外部电源电压施加到外部电源电源线时，内部电路中的升压电路会提升内部电源电压源的内部源电压。 当升压电路根据外部电源电压提升内部源电压时，外部源电压在升压阶段的早期阶段瞬间大于内部源电压。 第一电容元件限制电流从晶闸管整流电路的第二端子流到内部源极电压，即使在升压电路的早期阶段，当外部电源电压瞬时地大于升压阶段的内部源极电压时， 根据外部源电压提升内部源电压。 这样可以防止晶闸管整流电路发生故障并导通。

公开(公告)号：US20060049466A1

公开(公告)日：2006-03-09

申请号：US11082922

申请日：2005-03-18

Applicant: Noboru Egawa ,  Yasuhiro Fukuda

Inventor： Noboru Egawa ,  Yasuhiro Fukuda

IPC: H01L29/94

CPC classification number: H01L23/5258 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a semiconductor substrate, an insulating layer, a fuse, a diffusion layer and a resistor. The semiconductor substrate has a first conductivity type. The insulating layer is selectively formed on the surface of the semiconductor substrate. The fuse is formed on the insulating layer. The diffusion layer has a second conductivity type. The diffusion layer is formed on the surface of the semiconductor substrate and electrically connected to the fuse. The first resistor is electrically connected to the fuse.

Abstract translation: 具有半导体衬底，绝缘层，熔丝，扩散层和电阻器的半导体器件。 半导体衬底具有第一导电类型。 绝缘层选择性地形成在半导体衬底的表面上。 保险丝形成在绝缘层上。 扩散层具有第二导电类型。 扩散层形成在半导体衬底的表面上并与熔丝电连接。 第一个电阻器与保险丝电连接。

公开(公告)号：US06549198B1

公开(公告)日：2003-04-15

申请号：US09456816

申请日：1999-12-08

Applicant: Yoshiyuki Uto ,  Takafumi Esaki ,  Hiroshi Furukawa ,  Yasuhiro Fukuda

Inventor： Yoshiyuki Uto ,  Takafumi Esaki ,  Hiroshi Furukawa ,  Yasuhiro Fukuda

IPC: G09G500

CPC classification number: G09G1/167 ,  G09G2340/0478 ,  H04N5/126 ,  H04N5/46

Abstract: Disclosed is a HOUT position control circuit used to control the horizontal position of display image in a multisync monitor. The circuit has: a first PLL circuit that is phase-locked with input horizontal synchronous signal; a second PLL circuit that is phase-locked with output of the first PLL circuit; and a circuit for generating a delay between outputs of the first PLL circuit and the second PLL circuit to control the delay amount from the input horizontal synchronous signal to output horizontal drive signal.

Abstract translation: 公开了用于控制多同步监视器中的显示图像的水平位置的HOUT位置控制电路。 该电路具有：与输入水平同步信号锁相的第一个PLL电路; 与所述第一PLL电路的输出锁相的第二PLL电路; 以及用于在第一PLL电路和第二PLL电路的输出之间产生延迟以控制从输入水平同步信号到输出水平驱动信号的延迟量的电路。

公开(公告)号：US06495592B1

公开(公告)日：2002-12-17

申请号：US09609310

申请日：2000-06-30

Applicant: Shinya Yamashita ,  Jiro Takeo ,  Shuji Jinno ,  Yasuyo Kogure ,  Hiroyuki Onuki ,  Takaaki Okita ,  Junichiro Hata ,  Yasuhiro Fukuda ,  Naomi Ohtsuka

Inventor： Shinya Yamashita ,  Jiro Takeo ,  Shuji Jinno ,  Yasuyo Kogure ,  Hiroyuki Onuki ,  Takaaki Okita ,  Junichiro Hata ,  Yasuhiro Fukuda ,  Naomi Ohtsuka

IPC: A61K31335

CPC classification number: C07D337/14 ,  A61K31/352 ,  A61K31/382 ,  C07D313/14 ,  Y10S514/826

Abstract: The present invention offers a tracheal smooth muscle relaxant containing the compound represented by the following formula (1) or pharmacologically acceptable salt thereof as an effective ingredient.

Abstract translation: 本发明提供含有下述式（1）表示的化合物或其药理学可接受的盐作为有效成分的气管平滑肌松弛剂。

公开(公告)号：US06239958B1

公开(公告)日：2001-05-29

申请号：US09215146

申请日：1998-12-18

Applicant: Katsuhiro Kato ,  Yasuhiro Fukuda

Inventor： Katsuhiro Kato ,  Yasuhiro Fukuda

IPC: H02H900

CPC classification number: G11C7/24 ,  G11C11/4076 ,  G11C11/4078 ,  H01L27/0251 ,  H01L27/0266

Abstract: When a semiconductor integrated device is in an inactive state without being supplied with electric power, depletion type NMOS transistors act as resistors whereby a signal line connected to an input pad is electrically connected to the sources of input transistors via the NMOS transistors. In this situation, if an electrostatic surge is applied to the input pad, the surge is released to a voltage supply line. This ensures that the semiconductor integrated device is prevented from being damaged by the electrostatic surge. When electric power is supplied to the semiconductor integrated device and it becomes active, the NMOS transistors come to behave as insulating elements and thus these NMOS transistors have no adverse effects on the normal operation of the semiconductor integrated device.

Abstract translation: 当半导体集成器件处于无源状态而不提供电源时，耗尽型NMOS晶体管用作电阻器，由此连接到输入焊盘的信号线经由NMOS晶体管电连接到输入晶体管的源极。 在这种情况下，如果对输入焊盘施加静电浪涌，则浪涌被释放到电源线。 这确保了半导体集成器件被防止被静电浪涌损坏。 当向半导体集成器件提供电力并且其变为有效时，NMOS晶体管表现为绝缘元件，因此这些NMOS晶体管对半导体集成器件的正常工作没有不利影响。

公开(公告)号：US5850094A

公开(公告)日：1998-12-15

申请号：US749357

申请日：1996-11-20

Applicant: Katsuhiro Kato ,  Yasuhiro Fukuda

Inventor： Katsuhiro Kato ,  Yasuhiro Fukuda

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H03K17/08 ,  H03K17/0814 ,  H03K17/12 ,  H01L23/62

CPC classification number: H03K17/08142

Abstract: The present invention relates to a semiconductor device which utilizes a first conduction MOS output transistor 11 as an output transistor. The inventive semiconductor device have a advantage that the occupied area of an electrostatic breakdown preventing circuit is smaller than that of the conventional device, and the resistance against the electrostatic breakdown is better than that of the conventional device, and further an additional manufacturing process is not required, thereby obtaining the semiconductor device with an improved resistance. The inventive device is formed that a second conduction MOS transistor 13 functions as an electrostatic breakdown preventing circuit, with a drain of which being connected to an output terminal 15, and connected in a parallel form with the output transistor.

Abstract translation: 本发明涉及利用第一导电MOS输出晶体管11作为输出晶体管的半导体器件。 本发明的半导体器件具有静电击穿防止电路的占用面积小于常规器件的占用面积，并且抗静电击穿的电阻优于常规器件，并且另外的附加制造工艺不是 从而获得具有改进电阻的半导体器件。 本发明的器件形成为第二导通MOS晶体管13用作静电击穿防止电路，其漏极连接到输出端子15并且与输出晶体管并联连接。