公开(公告)号：US6002712A

公开(公告)日：1999-12-14

申请号：US898493

申请日：1997-07-22

申请人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

IPC分类号： H03H17/02 ,  H03H17/08 ,  H04B3/06 ,  H04L7/02 ,  H04L27/22 ,  H04B1/38 ,  H03K5/159

CPC分类号： H04L7/0029 ,  H04L7/0087 ,  H04L7/007

摘要： The present invention discloses a timing phase control apparatus which is particularly suitable for use in a modem used for very high speed data transmission employing a metallic line. The timing phase control apparatus includes a timing phase extracting portion to extract timing phase information from an input signal, a timing phase control filter portion to make a timing phase control to the input signal depending upon the timing phase information from the timing phase extracting portion through filter processing using a coefficient operation having a preset impulse response characteristic, and a filter processing coefficient determining portion to determine a coefficient used for the filter processing in the timing phase control filter portion depending upon the timing phase information and information about an approximate expression of the impulse response characteristic. An accuracy of a tap coefficient can be improved while reducing an amount of information about the tap coefficient, which should be stored.

摘要翻译： 本发明公开了一种定时相位控制装置，其特别适用于采用金属线路进行超高速数据传输的调制解调器。 定时相位控制装置包括定时相位提取部分，用于从输入信号提取定时相位信息;定时相位控制滤波器部分，用于根据来自定时相位提取部分的定时相位信息对输入信号进行定时相位控制， 使用具有预设脉冲响应特性的系数操作的滤波处理和滤波处理系数确定部分，以根据定时相位信息确定用于定时相位控制滤波器部分中的滤波处理的系数，以及关于近似表达式的信息 脉冲响应特性。 可以减少抽头系数的精度，同时减少应该存储的抽头系数的信息量。

公开(公告)号：US6078624A

公开(公告)日：2000-06-20

申请号：US829065

申请日：1997-03-31

申请人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa ,  Yuri Nigaki

发明人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa ,  Yuri Nigaki

IPC分类号： H04L27/18 ,  H04L25/03 ,  H04L25/497 ,  H04L5/12 ,  H04L23/02

CPC分类号： H04L25/4975 ,  H04L25/03343 ,  H04L25/497

摘要： A preceding apparatus for calculating a difference between an inputted signal point and an output signal obtained one timing before and outputting the difference has a position information judging unit for judging which position on a vector plane the output signal obtained one timing before is located in, and a signal point selecting storage for outputting any signal point among a plurality of signal points generated correspondingly to a signal point inputted from the outside with a result of the judgement fed form the position information judging unit nd the signal point inputted from the outside as an address, thereby decreasing the number of cycles required by a DSP process and realizing a precoder process in a degree achieved hitherto.

摘要翻译： 一种用于计算输入信号点和之前获得的一个定时之前的输出信号之间的差并输出该差的先前装置具有位置信息判断单元，用于判断向量平面上哪一个位置在一个定时获得的输出信号，以及 信号点选择存储器，用于输出与从外部输入的信号点相对应地生成的多个信号点中的任何信号点，其中从位置信息判断单元输入的判断结果将从外部输入的信号点作为地址 ，从而减少了DSP处理所需的周期数，并实现了迄今为止所达到的程度的预编码器处理。

公开(公告)号：US5537437A

公开(公告)日：1996-07-16

申请号：US505479

申请日：1995-07-21

申请人： Takashi Kaku ,  Hiroyasu Murata ,  Noboru Kawada ,  Kyoko Hirao ,  Hideo Miyazawa ,  Yuri Nigaki

发明人： Takashi Kaku ,  Hiroyasu Murata ,  Noboru Kawada ,  Kyoko Hirao ,  Hideo Miyazawa ,  Yuri Nigaki

IPC分类号： H04B3/10 ,  H04L7/04 ,  H04L27/01 ,  H04L27/22 ,  H03H7/30

CPC分类号： H04L7/041 ,  H04L7/046

摘要： A modulation and demodulation system suitable for use with a modem (modulator and demodulator apparatus) of a first polling type. The system allows reproduction of a signal necessary for initialization of a reception section of a modulator and demodulator apparatus with certainty in a short training time. The modulation and demodulation system is constructed such that, upon transmission of data, training data of a particular pattern are modulated and transmitted prior to transmission of the data, and such training data are demodulated by demodulation means and initialization of a reception section of the modulation and demodulation system is performed using the demodulation training data. The pattern of the training data to be transmitted includes an arrangement of signals wherein signals having phases different by 180.degree. from each other are arranged alternately, and a signal having the same phase as the last signal is arranged intermediately.

摘要翻译： 适用于第一轮询类型的调制解调器（调制器和解调器装置）的调制和解调系统。 该系统允许在短时间内确定地再现调制器和解调器装置的接收部分的初始化所需的信号。 调制和解调系统被构造成使得在传输数据时，在传输数据之前对特定模式的训练数据进行调制和发送，并且这样的训练数据由解调装置解调并且调制的接收部分的初始化 并且使用解调训练数据执行解调系统。 要发送的训练数据的模式包括信号的布置，其中具有彼此相差180°的相位的信号交替布置，并且具有与最后信号相同相位的信号被布置在中间。

公开(公告)号：US06377647B1

公开(公告)日：2002-04-23

申请号：US09205804

申请日：1998-12-04

申请人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

IPC分类号： H03D324

CPC分类号： H03L7/091 ,  H04L7/0331

摘要： A PLL circuit that causes an internal oscillation signal to lock to an external input clock signal, and is capable of suppressing jitter. The PLL circuit includes a frequency dividing circuit for frequency-dividing an input clock signal; a voltage-controlled oscillator; a missing-pulse clock signal creation circuit for creating, based on an output signal of the voltage-controlled oscillator, a missing-pulse clock signal having a higher speed than that of an output signal of the frequency dividing circuit and having a periodic missing-pulse portion; a phase comparator circuit for sampling the output signal of the frequency dividing circuit by using the missing-pulse clock signal; a shift register for storing a change in the output signal of the phase comparator circuit; and a digital signal processing circuit for converting a value stored in the shift register into a phase difference, and for controlling the input voltage to the voltage-controlled oscillator based on the phase difference.

摘要翻译： PLL电路使内部振荡信号锁定到外部输入时钟信号，并且能够抑制抖动。 PLL电路包括用于对输入时钟信号进行分频的分频电路; 压控振荡器; 一个缺失脉冲时钟信号产生电路，用于根据压控振荡器的输出信号创建一个具有比分频电路的输出信号高的缺失脉冲时钟信号， 脉冲部分 相位比较器电路，用于通过使用缺失脉冲时钟信号对分频电路的输出信号进行采样; 移位寄存器，用于存储相位比较器电路的输出信号的变化; 以及数字信号处理电路，用于将存储在移位寄存器中的值转换为相位差，并且用于基于相位差控制到压控振荡器的输入电压。

公开(公告)号：US5963593A

公开(公告)日：1999-10-05

申请号：US825067

申请日：1997-03-27

申请人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa ,  Yuri Nigaki

发明人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa ,  Yuri Nigaki

IPC分类号： H03H17/00 ,  H04B3/04 ,  H04B3/10 ,  H03H7/40 ,  H03H5/00

CPC分类号： H04B3/04 ,  H04L25/03885

摘要： A method of controlling a line equalizer such as a modem includes an extracting step of extracting plural tone signals each superimposed on a transmission signal and having a specific frequency component; a judging step of judging levels of the extracted tone signals; and a controlling step of controlling characteristic of a line equalizer which equalizes a receive signal, based on the levels of the judged tone signals. A line equalizer is controlled without performing an exchange of a training signal prior to starting a data transmission and without increasing the amount of hardware of a modem or the like.

摘要翻译： 一种控制诸如调制解调器之类的线路均衡器的方法包括一个提取步骤，提取叠加在传输信号上并具有特定频率分量的多个音调信号; 判断步骤，用于判断所提取的音调信号的电平; 以及控制步骤，基于所判断的音调信号的电平来控制均衡接收信号的线均衡器的特性。 在开始数据传输之前不必执行训练信号的交换，而不增加调制解调器等的硬件量，可以控制线路均衡器。

公开(公告)号：US5757865A

公开(公告)日：1998-05-26

申请号：US553990

申请日：1995-11-06

申请人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

IPC分类号： H04L27/38 ,  H04L27/00 ,  H04L27/22 ,  H04L27/233 ,  H04L27/06

CPC分类号： H04L27/2332 ,  H04L2027/003 ,  H04L2027/0055

摘要： The invention provides a carrier phase control circuit which can eliminate a phase intercept fluctuation so that, when the carrier phase control circuit is applied to a very high speed modem having a communication speed of, for example, 28.8 kbps, occurrence of a communication error can be suppressed and the modem has an improved characteristic. The carrier phase control circuit is provided on a reception side of a communication apparatus and interposed between an automatic equalizer and a signal decision section. The carrier phase control circuit includes a frequency offset removal section for predicting and removing an offset of a frequency of a transmission signal based on an output of the automatic equalizer, and a phase intercept variation removal section for predicting and removing a phase intercept variation of the transmission signal based on an output of the frequency offset removal section and inputting a resulted signal as an output thereof to the signal decision section.

摘要翻译： 本发明提供了一种载波相位控制电路，其可以消除相位截距波动，使得当载波相位控制电路被应用于具有例如28.8kbps的通信速度的非常高速的调制解调器时，可能发生通信错误 被抑制，调制解调器具有改进的特性。 载波相位控制电路设置在通信装置的接收侧，并插入在自动均衡器和信号判定部分之间。 载波相位控制电路包括：频率偏移消除部分，用于基于自动均衡器的输出来预测和去除发送信号频率的偏移;相位截距变化去除部分，用于预测和去除发送信号的相位截距变化， 基于频率偏移去除部的输出的发送信号，并将得到的信号作为其输出输入到信号判定部。

公开(公告)号：US06448861B2

公开(公告)日：2002-09-10

申请号：US09788841

申请日：2001-02-20

申请人： Noboru Kawada ,  Takashi Kaku ,  Takeshi Asahina ,  Tohru Ogawa ,  Hideo Miyazawa

发明人： Noboru Kawada ,  Takashi Kaku ,  Takeshi Asahina ,  Tohru Ogawa ,  Hideo Miyazawa

IPC分类号： H03L706

CPC分类号： H03L7/091 ,  H03L7/093

摘要： A limiter is connected with the output of a PLL to limit the amplitude of the output from the PLL. The output from limiter is supplied to a voltage-controlled oscillator (VCXO). The limiter determines the difference between the input signal and the output signal. If the difference exceeds a predetermined value, the change in the output from the limiter is limited to the predetermined value. If the difference does not exceed the predetermined value, the change in the output is considered to be a difference value.

摘要翻译： 限幅器与PLL的输出端相连以限制PLL输出的幅度。 限幅器的输出被提供给压控振荡器（VCXO）。 限幅器确定输入信号和输出信号之间的差异。 如果差异超过预定值，则限制器的输出的变化被限制为预定值。 如果该差异不超过预定值，则输出的变化被认为是差值。

公开(公告)号：US6026122A

公开(公告)日：2000-02-15

申请号：US925495

申请日：1997-09-09

申请人： Takashi Kaku ,  Kyoko Hirao ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Kyoko Hirao ,  Hideo Miyazawa

IPC分类号： H03H15/00 ,  H03H17/00 ,  H03H21/00 ,  H03M13/23 ,  H04B3/04 ,  H04L25/03 ,  H04L27/34 ,  H04L5/12 ,  H04L23/02

CPC分类号： H04L27/3411 ,  H04L25/03343 ,  H04L25/4975 ,  H04L27/34

摘要： A transfer process in which, an original vector signal is precoded to an intermediately-precoded vector signal, and the extended modulo operation is performed when the intermediately-precoded vector signal is located outside a predetermined extended-modulo limit area, and the precoded vector signal is transferred through a system having a predetermined filtering characteristic. From the transferred vector signal, the original vector signal is detected, based on a relationship between the vector components of the original vector signal and the transferred vector signal.

摘要翻译： 原始矢量信号被预编码为中间预编码矢量信号的传送处理，当中间预编码矢量信号位于预定的扩展模数限制区域之外时执行扩展模运算，并且预编码矢量信号 通过具有预定滤波特性的系统传送。 根据传送的矢量信号，基于原始矢量信号的矢量分量与传送的矢量信号之间的关系来检测原始矢量信号。

公开(公告)号：US5719907A

公开(公告)日：1998-02-17

申请号：US534161

申请日：1995-09-26

申请人： Takashi Kaku ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Hideo Miyazawa

IPC分类号： H04B3/04 ,  H04B3/06 ,  H04L1/20 ,  H04L25/02 ,  H04L25/08 ,  H04L27/22 ,  H04L27/38 ,  H04L25/38 ,  H04L5/16

CPC分类号： H04L27/3872 ,  H04L1/205

摘要： The invention provides a phase jitter extraction circuit and a phase jitter cancellation circuit for use with a reception section of a communication apparatus such as a modem used to transmit data using a telephone line or a private line, which are improved in that noise of a signal is prevented from increasing to suppress phase jitters with a high degree of accuracy and high noise components can be suppressed irrespective of the power of the input signal. The phase jitter extraction circuit includes a phase jitter detection section for detecting phase jitters from input/output information of a signal discriminator, a phase jitter forecasting section for forecasting phase jitters which will be produced later from the phase jitters detected by the phase jitter detection section, a selector for selectively outputting the phase jitters detected by the phase jitter detection section or the forecast phase jitters obtained by the phase jitter forecasting section, and a selector control section for discriminating a region of signal points received by the communication apparatus by way of a transmission line and controlling the selector in accordance with a result of the discrimination.

摘要翻译： 本发明提供一种相位抖动提取电路和相位抖动消除电路，用于与诸如调制解调器之类的通信装置的接收部分一起使用，该调制解调器用于使用电话线路或专用线路传输数据， 防止增加以高精度抑制相位抖动，并且与输入信号的功率无关，可以抑制高噪声分量。 相位抖动提取电路包括：相位抖动检测部分，用于从信号鉴别器的输入/输出信息中检测相位抖动;相位抖动预测部分，用于预测稍后将由相位抖动检测部分检测的相位抖动产生的相位抖动; 选择器，用于选择性地输出由相位抖动检测部分检测的相位抖动或由相位抖动预测部分获得的预测相位抖动，以及选择器控制部分，用于通过通信装置接收的信号点的区域 传输线，并根据鉴别结果控制选择器。

公开(公告)号：US5559799A

公开(公告)日：1996-09-24

申请号：US108536

申请日：1993-08-19

申请人： Hiroyasu Murata ,  Hideo Miyazawa ,  Takashi Kaku

发明人： Hiroyasu Murata ,  Hideo Miyazawa ,  Takashi Kaku

IPC分类号： H04L27/00 ,  H04L5/06 ,  H04L27/22 ,  H04L27/233 ,  H04L27/38 ,  H04B1/38 ,  H04J1/14

CPC分类号： H04L5/06 ,  H04L27/2338

摘要： A modulator and demodulator apparatus for use with a network is provided. The modulator and demodulator apparatus comprises a modulation section which includes a timing phase discrimination section for receiving, as an input signal thereto, a demodulation vector signal sampled into a digital value and discriminating to which one of a plurality of regions of a discrimination plane the phase of the input signal belongs. The timing phase discrimination section supplies, as an input to a next processing stage, a rotation vector obtained by rotating an input vector, moves the rotation vector to a quadrant which includes a reference discrimination region of the discrimination plane and performs, when the vector after the movement is not in the reference discrimination region, a predetermined calculation. When the vector after the movement comes to the reference discrimination region, another calculation is performed. This discriminates a timing phase of the input vector from the result of the calculation.

摘要翻译： 提供一种用于网络的调制器和解调器装置。 调制器和解调器装置包括调制部分，其包括定时相位鉴别部分，用于将采样成数字值的解调矢量信号作为输入信号，并将鉴别面的多个区域中的哪一个区分为相位 的输入信号属于。 定时相位识别部将作为输入向下一个处理级的输入提供通过旋转输入矢量而获得的旋转矢量，将旋转矢量移动到包括鉴别面的参考识别区域的象限，并且当后向量 运动不在参考识别区域中，所以是预定的计算。 当运动之后的矢量进入参考识别区域时，进行另一次计算。 这样就从计算结果中辨别出输入向量的定时相位。