公开(公告)号：US08458545B2

公开(公告)日：2013-06-04

申请号：US12955354

申请日：2010-11-29

申请人： Tanmoy Roy ,  Harsh Rawat ,  Swapnil Bahl ,  Amit Chhabra ,  Nitin Jain ,  Jatin Fultaria

发明人： Tanmoy Roy ,  Harsh Rawat ,  Swapnil Bahl ,  Amit Chhabra ,  Nitin Jain ,  Jatin Fultaria

IPC分类号： G01R31/28

CPC分类号： G11C29/42 ,  G11C29/024

摘要： A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.

摘要翻译： 电路包括被配置为接收测试地址输入信号的输入节点和经配置以从测试地址输入信号的第一部分产生选择要测试的电路的第一部分的第一地址的第一地址信号的电路 并且还从测试地址输入信号的第二部分生成被配置为选择要测试的电路的第二部分的第二信号。 然后将测试电路配置为在测试模式下使用第一个地址和第二个部分。

公开(公告)号：US20120137188A1

公开(公告)日：2012-05-31

申请号：US12955354

申请日：2010-11-29

申请人： Tanmoy Roy ,  Harsh Rawat ,  Swapnil Bahl ,  Amit Chhabra ,  Nitin Jain ,  Jatin Fultaria

发明人： Tanmoy Roy ,  Harsh Rawat ,  Swapnil Bahl ,  Amit Chhabra ,  Nitin Jain ,  Jatin Fultaria

IPC分类号： G01R31/28

CPC分类号： G11C29/42 ,  G11C29/024

摘要： A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.

摘要翻译： 电路包括被配置为接收测试地址输入信号的输入节点和经配置以从测试地址输入信号的第一部分产生选择要测试的电路的第一部分的第一地址的第一地址信号的电路 并且还从测试地址输入信号的第二部分生成被配置为选择要测试的电路的第二部分的第二信号。 然后将测试电路配置为在测试模式下使用第一个地址和第二个部分。

公开(公告)号：US20140173649A1

公开(公告)日：2014-06-19

申请号：US14126739

申请日：2012-06-19

申请人： Arun Kumar Medapati ,  Amit Chhabra ,  Srinivas Chandupatla

发明人： Arun Kumar Medapati ,  Amit Chhabra ,  Srinivas Chandupatla

IPC分类号： H04N21/254

CPC分类号： H04N21/2541 ,  H04N5/783 ,  H04N5/913 ,  H04N21/4384

摘要： A method and apparatus is described to achieve a fast service change. The method includes: receiving a plurality of transport streams at a client device, each transport stream including a plurality of encrypted services; decrypting an encrypted service from the plurality of encrypted services thereby forming a decrypted service; playing out the decrypted service; storing a portion of at least one encrypted service from the plurality of encrypted services in a storage device; receiving a request for displaying a different encrypted service; identifying a stored portion of the different encrypted service; decrypting the stored portion of the different encrypted service thereby forming a decrypted stored portion; playing out the decrypted stored portion of the different encrypted service at a faster than real time speed; storing a subsequent portion of the different encrypted service in the storage device, the subsequent portion corresponding to a subsequent portion of the different encrypted service received during the decrypting of the stored portion and the playing out the decrypted stored portion of the different encrypted service; decrypting the subsequent stored portion of the different encrypted service thereby forming a decrypted subsequent portion; and playing out the decrypted subsequent portion of the different encrypted service for display upon completion of the playing out of the decrypted stored portion.

摘要翻译： 描述了实现快速服务改变的方法和装置。 该方法包括：在客户端设备处接收多个传输流，每个传输流包括多个加密服务; 从所述多个加密服务解密加密服务，从而形成解密服务; 播放解密服务; 将来自所述多个加密服务的至少一个加密服务的一部分存储在存储设备中; 接收显示不同加密服务的请求; 识别不同加密服务的存储部分; 解密存储的不同加密服务部分，从而形成解密的存储部分; 以比实时速度快的速度播放不同加密服务的解密存储部分; 将所述不同加密服务的后续部分存储在所述存储设备中，所述后续部分对应于在所述存储部分的解密期间接收的所述不同加密服务的后续部分，以及播放所述不同加密服务的解密存储部分; 解密所述不同加密服务的后续存储部分，从而形成解密的后续部分; 以及在解密的存储部分的播放完成时播放不同加密服务的解密后续部分以进行显示。

公开(公告)号：US08381049B2

公开(公告)日：2013-02-19

申请号：US12814664

申请日：2010-06-14

申请人： Amit Chhabra

发明人： Amit Chhabra

IPC分类号： G11C29/00 ,  G01R31/28

CPC分类号： G11C29/022 ,  G11C29/12015

摘要： A system for testing faults in shadow logic includes a sequential block coupled to a shadow logic block and a delaying block to receive test patterns for testing the shadow logic block. The delaying block delays the test patterns by an access time of the sequential block to generate delayed test patterns. The delayed test patterns are passed to the shadow logic block for testing faults.

摘要翻译： 用于测试阴影逻辑中的故障的系统包括耦合到阴影逻辑块的顺序块和延迟块以接收用于测试阴影逻辑块的测试模式。 延迟块通过顺序块的访问时间来延迟测试模式以产生延迟的测试模式。 延迟的测试图案被传递到阴影逻辑块，用于测试故障。