公开(公告)号：US07689643B2

公开(公告)日：2010-03-30

申请号：US11262496

申请日：2005-10-27

申请人： Tarun Kumar Vashishta ,  Priyanka Agarwal

发明人： Tarun Kumar Vashishta ,  Priyanka Agarwal

IPC分类号： G06F7/50

CPC分类号： G06F7/5055 ,  G06F7/5057

摘要： An area efficient realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs, utilizing N LUTs with single output generation capability. It includes three inputs from every LUT for addition/subtraction, without any requirement for extra logic for support of arithmetic mode and carry chains. For FPGAs supporting 4-input LUTs, the concept is further enhanced with the capability to perform addition and subtraction dynamically, by exploiting the fourth unused input of the LUTs. Another embodiment involves delay-optimized realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs with 4-input LUTs. LUTs in the implementation have single output generation capability without any carry generation and propagation. The implementation utilizes N+1 LUTs and gives a delay proportional to N/2 of routing resource used. However, the implementation becomes more efficient by the use of cascade chains. The delay optimization is achieved by doing computation in two parallel chains.

摘要翻译： 在FPGA上实现的N位常数系数加法器/减法器的区域有效实现，利用具有单输出生成能力的N个LUT。 它包括来自每个LUT的三个输入用于加法/减法，而不需要额外的逻辑来支持算术模式和进位链。 对于支持4输入LUT的FPGA，通过利用LUT的第四个未使用的输入，动态地执行加法和减法的能力进一步增强了概念。 另一个实施例涉及在具有4输入LUT的FPGA上实现的N位常数系数加法器/减法器的延迟优化实现。 实现中的LUT具有单输出生成能力，无需任何进位生成和传播。 该实现使用N + 1个LUT并给出与所使用的路由资源的N / 2成比例的延迟。 然而，通过使用级联链，实现变得更加有效。 延迟优化通过在两个并行链中进行计算来实现。