公开(公告)号：US5027005A

公开(公告)日：1991-06-25

申请号：US466951

申请日：1990-01-18

申请人： Tatsuaki Kitsuta ,  Isao Shimotsuhama ,  Yoshio Watanabe ,  Masahiro Tanaka ,  Shinichi Shiotsu ,  Kazumi Ogawa

发明人： Tatsuaki Kitsuta ,  Isao Shimotsuhama ,  Yoshio Watanabe ,  Masahiro Tanaka ,  Shinichi Shiotsu ,  Kazumi Ogawa

IPC分类号： H03K3/2885

CPC分类号： H03K3/2885

摘要： A logic circuit comprises a first terminal for receiving an input data signal, a second terminal for receiving a clock signal, a first latch circuit coupled to the first and second terminals for latching the input data signal responsive to the clock signal, a second latch circuit coupled to the first latch circuit for latching an output signal of the first latch circuit, a third terminal for outputting an output data signal which is output from the second latch circuit, and a selecting part coupled to the third terminal for selectively feeding back the output data signal to the first latch circuit in a first mode and for cutting off the feedback of the output data signal to the first latch circuit in a second mode, where the logic circuit operates as a toggle flip-flop in the first mode and operates as a delay flip-flop in the second mode. The input data signal received by the first terminal selectively identifies one of the two modes of the flip-flop.