公开(公告)号：US5027005A

公开(公告)日：1991-06-25

申请号：US466951

申请日：1990-01-18

申请人： Tatsuaki Kitsuta ,  Isao Shimotsuhama ,  Yoshio Watanabe ,  Masahiro Tanaka ,  Shinichi Shiotsu ,  Kazumi Ogawa

发明人： Tatsuaki Kitsuta ,  Isao Shimotsuhama ,  Yoshio Watanabe ,  Masahiro Tanaka ,  Shinichi Shiotsu ,  Kazumi Ogawa

IPC分类号： H03K3/2885

CPC分类号： H03K3/2885

摘要： A logic circuit comprises a first terminal for receiving an input data signal, a second terminal for receiving a clock signal, a first latch circuit coupled to the first and second terminals for latching the input data signal responsive to the clock signal, a second latch circuit coupled to the first latch circuit for latching an output signal of the first latch circuit, a third terminal for outputting an output data signal which is output from the second latch circuit, and a selecting part coupled to the third terminal for selectively feeding back the output data signal to the first latch circuit in a first mode and for cutting off the feedback of the output data signal to the first latch circuit in a second mode, where the logic circuit operates as a toggle flip-flop in the first mode and operates as a delay flip-flop in the second mode. The input data signal received by the first terminal selectively identifies one of the two modes of the flip-flop.

公开(公告)号：US4928024A

公开(公告)日：1990-05-22

申请号：US344405

申请日：1989-04-28

申请人： Isao Shimotsuhama ,  Shinji Emori ,  Yoshio Watanabe ,  Masaya Tamamura

发明人： Isao Shimotsuhama ,  Shinji Emori ,  Yoshio Watanabe ,  Masaya Tamamura

IPC分类号： H03K19/086 ,  H03K19/094

CPC分类号： H03K19/086 ,  H03K19/09436

摘要： An ECL transistor pair is connected in parallel with a third transistor. A complementary signal is applied to the transistor pair. A high level of a signal that is applied to the third transistor is effectively higher than a high level of the input to the pair of transistors; and a low level of the signal applied to the third transistor is effectively lower than the high level of the input to the pair of transistors. The low level input to the third transistor enables the ECL circuit to output the complementary input signal and assures high speed ECL operation. The high level of the input to the third transistor disables the ECL circuit from outputting the complementary input signal.

公开(公告)号：US4933576A

公开(公告)日：1990-06-12

申请号：US349076

申请日：1989-05-09

申请人： Masaya Tamamura ,  Shinji Emori ,  Yoshio Watanabe ,  Isao Shimotsuhama

发明人： Masaya Tamamura ,  Shinji Emori ,  Yoshio Watanabe ,  Isao Shimotsuhama

IPC分类号： H03K3/037 ,  H03K19/086 ,  H03K19/173

CPC分类号： H03K19/1735 ,  H03K19/0866 ,  H03K3/0372 ,  Y10S257/923

摘要： A gate array device forms an arbitray logic circuit depending on interconnections formed thereon, and comprises a semiconductor chip having an approximate rectangular shape, an input terminal region including a plurality of input terminals formed at a peripheral portion of the semiconductor chip, an output terminal region including a plurality of output terminals formed at a peripheral portion of the semiconductor chip, and a macro cell region including a plurality of macro cells formed at a central portion of the semiconductor chip. The macro cells include first macro cells and second macro cells, where each of the first macro cells include a minimum number of elements for forming a master part of a master-slave flip-flop circuit and each of the second macro cells include at least a minimum number of elements for forming a slave part of the master-slave flip-flop circuit. The first macro cells and the second macro cells make macro cell pairs and are regularly arranged within the macro cell region.

公开(公告)号：US5001361A

公开(公告)日：1991-03-19

申请号：US349251

申请日：1989-05-09

申请人： Masaya Tamamura ,  Shinji Emori ,  Yoshio Watanabe ,  Isao Shimotsuhama

发明人： Masaya Tamamura ,  Shinji Emori ,  Yoshio Watanabe ,  Isao Shimotsuhama

IPC分类号： H03K3/289

CPC分类号： H03K3/289

摘要： A master-slave flip-flop circuit is made up of a master part which holds a data signal responsive to a clock signal and outputs the held data signal in the form of complementary output signals, and a slave part which holds the complementary output signals responsive to the clock signal and outputs at least one of the held complementary output signals. The complementary output signals of the master part have a logic amplitude which is smaller than a logic amplitude of the output signal of the slave part to ensure correct operation even when the data signal and the clock signal have high frequencies.

公开(公告)号：US08217276B2

公开(公告)日：2012-07-10

申请号：US10410434

申请日：2003-04-10

申请人： Kentaro Fujii ,  Yoshio Watanabe ,  Toru Takebe

发明人： Kentaro Fujii ,  Yoshio Watanabe ,  Toru Takebe

IPC分类号： H05K1/03

CPC分类号： H05K3/462 ,  H05K3/064 ,  H05K3/321 ,  H05K3/386 ,  H05K3/423 ,  H05K3/4623 ,  H05K3/4647 ,  H05K3/4658 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2203/0733 ,  H05K2203/135 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A multilayer printed circuit board which can surely establish interlayer connection with low resistance. The multilayer printed circuit board comprises: a first substrate having a conductive pattern on one face and a non-penetration connection hole on the other face, for exposing the conductive pattern to outside; a second substrate having a conductive pattern formed on a face opposed to the other face of first substrate and a conductive bump on the conductive pattern integrally. The first substrate and the second substrate are integrated by engaging the bump of the second substrate with the connection hole of the first substrate and by intervening a conductive cement between the bumps and the conductive pattern exposed to outside from the connection holes.

摘要翻译： 一种多层印刷电路板，可以可靠地建立具有低电阻的层间连接。 所述多层印刷电路板包括：在一个面上具有导电图案的第一基板和另一面上的非穿透连接孔，用于将导电图案暴露于外部; 第二基板，其具有形成在与第一基板的另一面相对的表面上的导电图案和导电图案上的导电凸块。 第一基板和第二基板通过将第二基板的凸块与第一基板的连接孔接合并且通过在凸起和从连接孔露出到外部的导电图案之间插入导电粘合剂来集成。

公开(公告)号：US20100203842A1

公开(公告)日：2010-08-12

申请号：US12671302

申请日：2008-07-30

申请人： Koichi Tachikawa ,  Yoshio Watanabe

发明人： Koichi Tachikawa ,  Yoshio Watanabe

IPC分类号： H04B1/38

CPC分类号： H04B7/061

摘要： A wireless communication terminal apparatus 10 is comprised of a plurality of antennas Ant1 and Ant2, a switch circuit 11 for switching to one selected antenna among the plurality of antennas Ant1 and Ant2, for carrying out a communication, and a control unit 14 for selecting another antenna among antennas in a non-selection status in response to the status of the reception signal, in a case where a status of a reception signal of an antenna in a selection status is not in the predetermined condition, and regardless a status of the reception signal of the antennas in a non-selection status, and controlling the switch circuit for making the switching of another antenna in a non-selection status at a transmission.

摘要翻译： 无线通信终端装置10由多个天线Ant1和Ant2构成，切换电路11用于切换到多个天线Ant1和Ant2中的一个选定的天线，用于进行通信，以及控制单元14，用于选择另一天线 在选择状态的天线的接收信号的状态不在预定条件的情况下，响应于接收信号的状态，处于非选择状态的天线之间的天线，并且不管接收的状态如何 天线的信号处于非选择状态，并且控制开关电路，用于在另一个天线的切换中处于非选择状态。

公开(公告)号：US20060049130A1

公开(公告)日：2006-03-09

申请号：US11212684

申请日：2005-08-29

申请人： Yoshio Watanabe

发明人： Yoshio Watanabe

IPC分类号： H01B13/00 ,  H05K1/00

CPC分类号： H05K3/4611 ,  H05K1/0218 ,  H05K1/0393 ,  H05K1/16 ,  H05K3/4614 ,  H05K3/4635 ,  H05K2201/055 ,  H05K2201/0715 ,  Y10T29/49135 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A multilayer wiring board having a plurality of wiring layers is proposed, which is prepared by a process having the steps of: forming, on one insulating sheet, wiring patterns for all the wiring layers, which patterns are arranged at predetermined positions; and folding the insulating sheet having formed the wiring patterns in the predetermined order and stacking the folded sheet while positioning, and then heating the resultant sheet in a vacuum under a pressure to form a three-dimensional electric wiring.

摘要翻译： 提出了具有多个布线层的多层布线板，其通过以下步骤制备：具有以下步骤的方法：在一个绝缘片上形成用于所有布线层的布线图案，哪些图案布置在预定位置; 并且以预定的顺序折叠形成布线图案的绝缘片并定位时堆叠折叠片，然后在压力下在真空中加热所得的片以形成三维电布线。

公开(公告)号：US06670757B2

公开(公告)日：2003-12-30

申请号：US09358861

申请日：1999-07-22

申请人： Tetsuya Kato ,  Yoshio Watanabe ,  Hiroki Kono

发明人： Tetsuya Kato ,  Yoshio Watanabe ,  Hiroki Kono

IPC分类号： H01J1749

CPC分类号： H01J11/12 ,  H01J11/26 ,  H01J11/34 ,  H01J11/38 ,  H01J11/44 ,  H01J2211/444

摘要： A plasma display panel (“PDP”) is provided with a protrusion lower than barrier ribs on an inner surface of a back plate substrate, and a phosphor layer formed on a rib surface within a unitary emission unit including a surface of the protrusion, thereby realizing the PDP of high brightness, high luminous efficiency and long operating life. Also, the PDP has a structure, in which a portion of the inner surface of the substrate is opened to a discharge space directly or through a protective layer, so as to improve power consumption remarkably. Further, the invention provides a production of the PDP with superior whiteness by way of controlling a balance of each color with shape of the respective protrusions. Moreover, an electrode can be formed easily and precisely on an upper part of the protrusion by providing a sloped surface for at least one end in a longitudinal direction of the protrusion. As a result, the invention provides the PDP that is of low power consumption, high brightness, high luminous efficiency, and is capable of performing a speedy and stable electric-discharge and displaying white color of high color temperature.

摘要翻译： 等离子体显示面板（“PDP”）在后板基板的内表面上设置有比阻挡肋低的突起，以及形成在包括突起的表面的单位发射单元内的肋表面上的荧光体层，由此 实现高亮度，高发光效率和长使用寿命的PDP。 此外，PDP具有这样的结构，其中基板的内表面的一部分直接或通过保护层向放电空间开放，从而显着地提高功耗。 此外，本发明通过以各个突起的形状控制每种颜色的平衡来提供具有优异白度的PDP的生产。 此外，通过为突起的纵向方向上的至少一端提供倾斜表面，可以在突起的上部容易且精确地形成电极。 结果，本发明提供了低功耗，高亮度，高发光效率的PDP，能够进行快速稳定的放电和显示高色温的白色。

公开(公告)号：US06534227B2

公开(公告)日：2003-03-18

申请号：US09758193

申请日：2001-01-12

申请人： Toshiyuki Kabata ,  Toshio Fukagai ,  Junichi Yamazaki ,  Katsuhiko Tani ,  Noriyuki Iwata ,  Takuji Katoh ,  Yoshio Watanabe ,  Yuka Miyamoto

发明人： Toshiyuki Kabata ,  Toshio Fukagai ,  Junichi Yamazaki ,  Katsuhiko Tani ,  Noriyuki Iwata ,  Takuji Katoh ,  Yoshio Watanabe ,  Yuka Miyamoto

IPC分类号： G03F900

CPC分类号： G03G5/14 ,  G03G5/04 ,  G03G5/10

摘要： A photoreceptor including a support and a photosensitive layer formed thereon, optionally an undercoat layer between the support and the photosensitive layer, wherein when a group of data consisting of N samples of the height x(t)(&mgr;m) of a profile at the interface of the support on the side of the photosensitive layer, the interface of the photosensitive layer on the side of the support, and/or the interface of the undercoat layer on the side of the photosensitive layer, measured perpendicular to a horizontal direction of the support, taken at &Dgr;t(&mgr;m) intervals in the horizontal direction, is subjected to Fourier transformation in accordance with a formula as specified in the specification, in a power spectrum obtained by the Fourier transformation, I(S) represented by a formula specified in the specification has a particular value, a method of evaluating the above photoreceptor, a method of producing the photoreceptor, and an image formation apparatus in which the photoreceptor is incorporated are disclosed.

摘要翻译： 一种感光体，包括支撑体和形成在其上的感光层，任选地在支撑体和感光层之间的底涂层，其中当由界面处的轮廓的高度x（t）（母体）的N个样本组成的数据组 感光层一侧的支撑体，支撑体侧的感光层的界面和/或感光层一侧的底涂层的界面垂直于支撑体的水平方向测量 在水平方向以DELTAt（mum）间隔进行傅立叶变换，按照本说明书中规定的公式，在通过傅里叶变换获得的功率谱中进行傅里叶变换，其由式 规格具有特定价值，评价上述感光体的方法，感光体的制造方法和图像形成装置，其中感光体i 公开。

公开(公告)号：US06528952B2

公开(公告)日：2003-03-04

申请号：US10080585

申请日：2002-02-25

申请人： Tetsuya Kato ,  Kazuo Tomida ,  Yoshio Watanabe ,  Hiroki Kono

发明人： Tetsuya Kato ,  Kazuo Tomida ,  Yoshio Watanabe ,  Hiroki Kono

IPC分类号： G09G310

CPC分类号： H01J11/44 ,  G09G3/291 ,  G09G3/2965 ,  G09G3/2986 ,  H01J11/12 ,  H01J11/30 ,  H01J11/32 ,  H01J2211/323 ,  H01J2211/444

摘要： The PDP of the present invention has first, second and third electrodes. Intervals between the first and second electrode is 0.2 mm or more. A plurality of third electrodes are formed. Protrusions which are shorter than ribs are formed between the plurality of third electrodes. The plurality of third electrodes are connected, in part, to one another or at least connected in part, such that they form a network. In the driving method of the PDP of the present invention, a self-erasing discharge is generated, and subsequently when a potential difference between the electrodes is increased, using the self-erasing discharge as a trigger, discharge is generated and light is emitted.