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公开(公告)号：US20060002396A1
公开(公告)日：2006-01-05
申请号：US11170789
申请日：2005-06-30
申请人： Tatsuhiko Amagai , Yuichi Suzuki
发明人： Tatsuhiko Amagai , Yuichi Suzuki
IPC分类号： H04L12/28
CPC分类号： H04L12/5601 , H04L2012/5651 , H04L2012/5672
摘要： Sending priority of plural stages is statically assigned according to a quality class and an output connection, and the sending priority is dynamically changed according to a state of sending request stacking every sending priority and a state of ATM cell conversion processing of a frame, and ATM cell conversion request means for issuing an ATM cell conversion request is provided every output route, and the cell conversion processing of the frame is selected and performed in the order of higher sending priority every time one cell conversion.
摘要翻译： 根据质量等级和输出连接静态分配多级发送优先级，发送优先级根据每发送优先级发送请求堆叠的状态和帧的ATM信元转换处理状态以及ATM 每个输出路由都提供用于发出ATM信元转换请求的信元转换请求装置，并且每当一个信元转换时，以更高的发送优先级的顺序选择并执行该帧的信元转换处理。
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公开(公告)号：US08073006B2
公开(公告)日：2011-12-06
申请号：US11170789
申请日：2005-06-30
申请人： Tatsuhiko Amagai , Yuichi Suzuki
发明人： Tatsuhiko Amagai , Yuichi Suzuki
IPC分类号： H04J3/16
CPC分类号： H04L12/5601 , H04L2012/5651 , H04L2012/5672
摘要： Sending priority of plural stages is statically assigned according to a quality class and an output connection, and the sending priority is dynamically changed according to a state of sending request stacking every sending priority and a state of ATM cell conversion processing of a frame, and ATM cell conversion request means for issuing an ATM cell conversion request is provided every output route, and the cell conversion processing of the frame is selected and performed in the order of higher sending priority every time one cell conversion.
摘要翻译： 根据质量等级和输出连接静态分配多级发送优先级，发送优先级根据每发送优先级发送请求堆叠的状态和帧的ATM信元转换处理状态以及ATM 每个输出路由都提供用于发出ATM信元转换请求的信元转换请求装置，并且每当一个信元转换时，以更高的发送优先级的顺序选择并执行该帧的信元转换处理。
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3.发明授权Device with quality controllable SAR function by upper layer instruction, LSI unit and quality control method by upper layer instruction 失效通过上层指令，LSI单元和上层指令的质量控制方法，具有质量可控SAR功能的设备公开(公告)号：US06687250B1
公开(公告)日：2004-02-03
申请号：US09579508
申请日：2000-05-26
申请人： Yuichi Suzuki , Tatsuhiko Amagai
发明人： Yuichi Suzuki , Tatsuhiko Amagai
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04L2012/5651 , H04L2012/5658
摘要： A device with quality controllable SAR function according to upper layer instruction enables reassembly and segmentation SAR of AAL5 to which priority in upper layer is reflected to be provided in reassembly and segmentation of AAL5 in ATM layer processing. This device is provided with a frame storage unit for executing reassembly of a frame of AAL5 (ATM Adaptation Layer Type 5) from an ATM (Asynchronous Transfer Mode) cell, an identification adder for receiving a cell stream through a cell reassembly processor, and for adding an identifier on a basis of cell header information in order to introduce the cell which the frame storage unit receives therein into the frame storage unit or on the basis of upper layer information within a cell payload, a cell reassembly unit for assembling the cell received by the cell reassembly processor, a next processing decision unit having a second priority part for deciding either sending or abolition of the frame concerned on the basis of the received header on the occasion of sending the frame obtained from the cell received according to the cell reassembly processor and/or on the basis of the upper layer information within the payload, a storage unit for storing therein an inputted transmission frame, and a selector for selecting the transmission frame sent from the storage unit.
摘要翻译： 根据上层指令，具有质量可控的SAR功能的装置能够在ATM层处理中重新组合和分割AAL5，反映在上层优先级的AAL5的重组和分割SAR。 该设备具有帧存储单元，用于从ATM（异步传输模式）单元执行AAL5（ATM适配层类型5）的帧的重组，用于通过信元重组处理器接收信元流的识别加法器，以及用于 基于单元标题信息添加标识符，以便将帧存储单元在其中接收的单元引入到帧存储单元中，或者基于小区有效载荷内的上层信息，组合接收到的单元的单元重组单元 通过信元重组处理器，具有第二优先级部分的下一个处理决策单元，用于在发送从根据信元重新组合接收到的信元获得的帧的情况下，基于所接收的报头来决定所涉及的帧的发送或废除 处理器和/或基于有效载荷内的上层信息的存储单元，用于在其中存储输入的传输帧， 以及选择器，用于选择从存储单元发送的传输帧。
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公开(公告)号：US20120051367A1
公开(公告)日：2012-03-01
申请号：US13289610
申请日：2011-11-04
申请人： Tatsuhiko Amagai , Yuichi Suzuki
发明人： Tatsuhiko Amagai , Yuichi Suzuki
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L2012/5651 , H04L2012/5672
摘要： Sending priority of plural stages is statically assigned according to a quality class and an output connection, and the sending priority is dynamically changed according to a state of sending request stacking every sending priority and a state of ATM cell conversion processing of a frame, and ATM cell conversion request means for issuing an ATM cell conversion request is provided every output route, and the cell conversion processing of the frame is selected and performed in the order of higher sending priority every time one cell conversion.
摘要翻译： 根据质量等级和输出连接静态分配多级发送优先级，发送优先级根据每发送优先级发送请求堆叠的状态和帧的ATM信元转换处理状态以及ATM 每个输出路由都提供用于发出ATM信元转换请求的信元转换请求装置，并且每当一个信元转换时，以更高的发送优先级的顺序选择并执行该帧的信元转换处理。
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公开(公告)号：US06944182B1
公开(公告)日：2005-09-13
申请号：US09567442
申请日：2000-05-10
申请人： Tatsuhiko Amagai , Yuichi Suzuki
发明人： Tatsuhiko Amagai , Yuichi Suzuki
IPC分类号： H04Q3/00 , H04J3/16 , H04L12/28 , H04L12/865 , H04L12/951
CPC分类号： H04L12/5601 , H04L2012/5651 , H04L2012/5672
摘要： Sending priority of plural stages is statically assigned according to a quality class and an output connection, and the sending priority is dynamically changed according to a state of sending request stacking every sending priority and a state of ATM cell conversion processing of a frame, and ATM cell conversion request means for issuing an ATM cell conversion request is provided every output route, and the cell conversion processing of the frame is selected and performed in the order of higher sending priority every time one cell conversion.
摘要翻译： 根据质量等级和输出连接静态分配多级发送优先级，发送优先级根据每发送优先级发送请求堆叠的状态和帧的ATM信元转换处理状态以及ATM 每个输出路由都提供用于发出ATM信元转换请求的信元转换请求装置，并且每当一个信元转换时，以更高的发送优先级的顺序选择并执行该帧的信元转换处理。
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6.发明授权Segmentation and reassembly system for ATM communication network improved in throughput 失效ATM通信网络的分段和重组系统提高了吞吐量公开(公告)号：US06493356B1
公开(公告)日：2002-12-10
申请号：US09226242
申请日：1999-01-07
IPC分类号： H04J324
CPC分类号： H04L49/30 , H04L2012/5652 , H04L2012/5663
摘要： A segment and reassembly system cooperates with a data processing system for various kinds of data processing on ATM cells accumulated in frame buffers, and supplies ATM cells to ISDN after completion of various kinds of data processing; wherein the segment and reassembly system has processing units connected through exclusive interfaces to engines incorporated in the data processing system, and the engines process the pieces of data stored in the frame buffers at high speed, thereby improving the throughput of the segmentation and reassembly system.
摘要翻译： 段和重组系统与用于在帧缓冲器中累积的ATM信元的各种数据处理的数据处理系统配合，并且在完成各种数据处理之后将ATM信元提供给ISDN; 其中段和重组系统具有通过专用接口连接到并入数据处理系统中的引擎的处理单元，并且引擎以高速处理存储在帧缓冲器中的数据段，从而提高分段和重组系统的吞吐量。
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7.发明授权Router switches to old routing table when communication failure caused by current routing table and investigates the cause of the failure 有权路由器切换到旧路由表时，由当前路由表导致通信故障，并调查故障原因公开(公告)号：US06625659B1
公开(公告)日：2003-09-23
申请号：US09484459
申请日：2000-01-18
申请人： Tatsuo Aramizu , Tatsuhiko Amagai , Hiroshi Ikeda
发明人： Tatsuo Aramizu , Tatsuhiko Amagai , Hiroshi Ikeda
IPC分类号： G06F15173
摘要： Even when a communication failure happens to occur, the interrupted communication can be quickly recovered by a router apparatus. The router apparatus is comprised of: a plurality of routing tables into which new route information is stored every time route information is changed; a rewriting time saving unit for saving rewriting time information of the plurality of routing tables; a table switching unit for switching the plurality of routing tables; and a route processor unit for managing, for example, setting/rewriting/deleting the routing table based upon route information supplied by a network operator, or route information obtained by routing protocol. In this router apparatus, when a communication failure caused by the routing table occurs, the failed routing table is switched to another routing table into which old route information has been stored so as to continue the communication, and also, a communication trouble reason is investigated by comparing the route information before/after the failed routing table is switched.
摘要翻译： 即使发生通信故障，中断的通信也可以由路由器装置快速恢复。 路由器装置包括：多个路由表，每当路由信息改变时存储新的路由信息; 重写时间保存单元，用于保存多个路由表的重写时间信息; 用于切换所述多个路由表的表切换单元; 以及路由处理器单元，用于基于由网络运营商提供的路由信息或通过路由协议获得的路由信息来管理例如设置/重写/删除路由表。 在该路由器装置中，当发生由路由表引起的通信故障时，将故障路由表切换到已经存储了旧路由信息的另一路由表，以便继续通信，并且还调查通信故障原因 通过比较故障路由表切换之前/之后的路由信息。
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公开(公告)号：US06418145B1
公开(公告)日：2002-07-09
申请号：US09213931
申请日：1998-12-17
IPC分类号： H04L1256
CPC分类号： H04L69/16 , H04L29/06 , H04L69/161 , H04L69/168 , H04L69/22 , H04L2012/5658 , H04L2012/5667 , H04Q11/0478
摘要： An internet protocol (IP) layer processor has an IP header processing section for checking a defect in an IP header of a first ATM cell of an AAL5 frame, and a SAR (segregation and reassemblage) section for transferring the AAL5 frame in the form of separate ATM cells if the check by the IP header processing section indicates a normal IP header, without using a CPU. SAR notifies a defect in the IP header to CPU without transmission of the AAL5 frame if the check indicates the defect in the IP header. The IP layer processor achieves a higher processing due to the direct transfer by the SAR without using processing by a software.
摘要翻译： 互联网协议（IP）层处理器具有用于检查AAL5帧的第一ATM信元的IP报头中的缺陷的IP报头处理部分和用于传送AAL5帧的SAR（分离和重新组合）部分，其形式为 如果IP报头处理部分的检查指示正常的IP报头，而不使用CPU，则分离的ATM信元。 如果检查指示IP报头中的缺陷，则SAR将IP报头中的缺陷通知给CPU，而不传输AAL5帧。 IP层处理器由于SAR的直接传输而实现了更高的处理，而不用软件进行处理。
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公开(公告)号：US07970012B2
公开(公告)日：2011-06-28
申请号：US12395051
申请日：2009-02-27
CPC分类号： H04L12/5601 , H04L2012/5658 , H04L2012/5667
摘要： A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.
摘要翻译： 公开了一种用于通过多个层交换分组数据的分组处理方法，包括以下步骤：将整个分组存储到分组存储器; 并且将在多层的层2处理部分和层3处理部分的处理中使用的分组数据的每个分组的一部分存储到多端口共享存储器，层2处理部分和层3处理部分访问 多端口共享内存的内存空间相同。 此外，使用流水线处理系统，使得当层2处理部分和层3处理部分访问共享存储器时，它们不彼此干扰。
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公开(公告)号：US07515610B2
公开(公告)日：2009-04-07
申请号：US11537272
申请日：2006-09-29
CPC分类号： H04L12/5601 , H04L2012/5658 , H04L2012/5667
摘要： A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.
摘要翻译： 公开了一种用于通过多个层交换分组数据的分组处理方法，包括以下步骤：将整个分组存储到分组存储器; 并且将在多层的层2处理部分和层3处理部分的处理中使用的分组数据的每个分组的一部分存储到多端口共享存储器，层2处理部分和层3处理部分访问 多端口共享内存的内存空间相同。 此外，使用流水线处理系统，使得当层2处理部分和层3处理部分访问共享存储器时，它们不彼此干扰。
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