公开(公告)号：US06418145B1

公开(公告)日：2002-07-09

申请号：US09213931

申请日：1998-12-17

申请人： Kazuhiko Isoyama ,  Tatsuhiko Amagai ,  Toshiya Aramaki

发明人： Kazuhiko Isoyama ,  Tatsuhiko Amagai ,  Toshiya Aramaki

IPC分类号： H04L1256

CPC分类号： H04L69/16 ,  H04L29/06 ,  H04L69/161 ,  H04L69/168 ,  H04L69/22 ,  H04L2012/5658 ,  H04L2012/5667 ,  H04Q11/0478

摘要： An internet protocol (IP) layer processor has an IP header processing section for checking a defect in an IP header of a first ATM cell of an AAL5 frame, and a SAR (segregation and reassemblage) section for transferring the AAL5 frame in the form of separate ATM cells if the check by the IP header processing section indicates a normal IP header, without using a CPU. SAR notifies a defect in the IP header to CPU without transmission of the AAL5 frame if the check indicates the defect in the IP header. The IP layer processor achieves a higher processing due to the direct transfer by the SAR without using processing by a software.

摘要翻译： 互联网协议（IP）层处理器具有用于检查AAL5帧的第一ATM信元的IP报头中的缺陷的IP报头处理部分和用于传送AAL5帧的SAR（分离和重新组合）部分，其形式为 如果IP报头处理部分的检查指示正常的IP报头，而不使用CPU，则分离的ATM信元。 如果检查指示IP报头中的缺陷，则SAR将IP报头中的缺陷通知给CPU，而不传输AAL5帧。 IP层处理器由于SAR的直接传输而实现了更高的处理，而不用软件进行处理。

公开(公告)号：US06982975B1

公开(公告)日：2006-01-03

申请号：US09540990

申请日：2000-03-31

申请人： Toshiya Aramaki ,  Kazuhiko Isoyama

发明人： Toshiya Aramaki ,  Kazuhiko Isoyama

IPC分类号： H04Q11/04 ,  H04L12/56

CPC分类号： H04L49/1561 ,  H04L49/15 ,  H04L49/30 ,  H04L49/3081 ,  H04L2012/5649 ,  H04L2012/565

摘要： In a packet switch structured by connecting unit switches in multi-stages which is capable of transmitting packets without delay and accommodating high-speed lines, unit switches at the first stage assign, to an input packet, a sequence number according to a destination of the packet and distribute and send out the packet to a unit switch at the succeeding stage and unit switches at the final stage sequence and output packets according to sequence numbers assigned to packets received from a unit switch at the preceding stage.

摘要翻译： 在通过连接能够不延迟地发送分组并且容纳高速线路的多级的单元交换机构成的分组交换机中，第一级的单元交换机根据输入的目的地向输入分组分配序列号 分组并发送到后级单元交换机，并在最后阶段切换单元序列，并根据分配给前一单元交换机接收的分组的序列号输出分组。

公开(公告)号：US06570873B1

公开(公告)日：2003-05-27

申请号：US09438397

申请日：1999-11-12

申请人： Kazuhiko Isoyama ,  Toshiya Aramaki

发明人： Kazuhiko Isoyama ,  Toshiya Aramaki

IPC分类号： H04L1256

CPC分类号： H04L49/30 ,  H04L47/50 ,  H04L47/522 ,  H04L47/621 ,  H04L47/6215 ,  H04L49/205 ,  H04L49/254 ,  H04L2012/5651 ,  H04L2012/568 ,  H04L2012/5681 ,  H04Q11/0478

摘要： Disclosed is a system for scheduling reservation of traffic with priority, in which each of input ports detects the reserved addressed output port for a high priority traffic by detecting signaling of the traffic and notifies the reserved addressed output port to a scheduler, the scheduler sets a switch connection for passing the high priority traffic with priority every time slot and assigns other switch connections to best effort traffics, and when the switch connections are determined, outputs grant signals to input ports and setting signal to a switch.

摘要翻译： 公开了一种用于调度具有优先级的业务的预留的系统，其中每个输入端口通过检测业务的信令来检测用于高优先级业务的保留的寻址输出端口，并将保留的寻址的输出端口通知给调度器，调度器设置 交换机连接，用于每个时隙优先通过高优先级流量，并将其他交换机连接分配给尽力服务流量，并且当确定交换机连接时，输出向输入端口授予信号并将信号设置到交换机。

公开(公告)号：US6049527A

公开(公告)日：2000-04-11

申请号：US824051

申请日：1997-03-21

申请人： Kazuhiko Isoyama ,  Toshiya Aramaki

发明人： Kazuhiko Isoyama ,  Toshiya Aramaki

IPC分类号： H04Q3/00 ,  H04L12/801 ,  H04L12/823 ,  H04L12/851 ,  H04L12/911 ,  H04L12/927 ,  H04Q11/04 ,  H04L12/54 ,  H04L12/56

CPC分类号： H04Q11/0478 ,  H04L2012/5648 ,  H04L2012/5658 ,  H04L2012/5682

摘要： The present invention is to provide a cell discard control system for an ATM (asynchronous transfer mode) cell buffer capable of preventing useless cells which are not restored to an original packet from being transmitted to an ATM network and minimize a discarded number of packets which should not be discarded. It comprises a cell receiving section 11 having a packet identifier adding part 11a for adding a packet identifier for identifying being cellulated from the same packet for an input cell and a cell discard part 11b for discarding cells, a cell buffer 12 for buffering cells transferred from the cell receiving section 11, the cell transmitting section 13 for transmitting cells transferred from the cell buffer 12 to an ATM network and transmitting idle cells instead of discarded cell which have been discarded by a cell discard part 13a, and buffer controller 14 for detecting a packet identifier added to a cell being discarded due to over flow of the cell buffer 12 and instructing the cell receiving section 11 and the cell transmitting section 13 to discard cells having the same packet identifier being detected.

摘要翻译： 本发明提供一种用于ATM（异步传输模式）小区缓冲器的小区丢弃控制系统，其能够防止没有恢复到原始分组的无用小区被发送到ATM网络并且将丢弃的分组数量最小化 不被丢弃 它包括：具有分组标识符添加部分11a的小区接收部分1111，用于添加用于识别的分组标识符，用于从用于输入小区的相同分组中被识别;以及用于丢弃小区的小区丢弃部分11b;小区缓冲器12， 小区接收部分11，用于发送从小区缓冲器12传送到ATM网络的小区的小区发送部分13，并且发送空闲小区而不是被小区丢弃部分13a舍弃的丢弃小区，以及用于检测 分组标识符被添加到由于小区缓冲器12的过流而被丢弃的小区，并且指示小区接收部分11和小区发射部分13丢弃具有被检测到的相同分组标识符的小区。

公开(公告)号：US06680946B1

公开(公告)日：2004-01-20

申请号：US09302286

申请日：1999-04-30

申请人： Kazuhiko Isoyama ,  Toshiya Aramaki ,  Akira Arutaki

发明人： Kazuhiko Isoyama ,  Toshiya Aramaki ,  Akira Arutaki

IPC分类号： H04L1256

CPC分类号： H04L49/256 ,  H04L12/5601

摘要： A method for transferring a series of layer-3 packets through an ATM network composed of a plurality of ATM switches is disclosed. An ingress gateway determines whether a packet flow has been registered and, when the flow has not been registered, determines a transfer route. A connection setup cell is transmitted to a next-hop ATM switch to ensure a connection dedicated to transfer of tho series of packets. Then, a series of packets is transferred to the next-hop ATM switch through the connection after the connection has been set up.

摘要翻译： 公开了一种通过由多个ATM交换机组成的ATM网络传送一系列三层分组的方法。 入口网关确定分组流是否已经被注册，并且当流尚未被注册时，确定传输路由。 连接建立单元被发送到下一跳ATM交换机，以确保专门用于传送一系列数据包的连接。 然后，在连接建立后，一系列数据包通过连接传输到下一跳ATM交换机。

公开(公告)号：US06618760B1

公开(公告)日：2003-09-09

申请号：US09549707

申请日：2000-04-14

申请人： Toshiya Aramaki ,  Tsugio Okamoto

发明人： Toshiya Aramaki ,  Tsugio Okamoto

IPC分类号： G06F15173

CPC分类号： H04L45/00 ,  H04L45/7457

摘要： An improved method for retrieving next forwarding destination of a received data signal is disclosed. First, a plurality of first tables and a second table are stored in the retrieval table. The first tables are hierarchically arranged according to division of the destination address, an entry of each of the first tables including a second-table pointer indicating a next accessed second entry of the second table. The second table serves as an index table of the first tables. Each of entries of the second table includes a hop pointer and a first-table pointer indicating a next accessed first table. The second table and a selected one of the first tables are alternately accessed depending on a first-table pointer included in an accessed entry of the second table while retrieving an entry of an accessed first table using a corresponding divisional portion of the destination address. A hop pointer is read from a finally accessed entry of the second table as a retrieval result.

摘要翻译： 公开了一种用于检索接收到的数据信号的下一转发目的地的改进方法。 首先，将多个第一表和第二表存储在检索表中。 第一表根据目的地址的划分被分层排列，每个第一表的条目包括指示第二表的下一个被访问的第二条目的第二表指针。 第二个表用作第一个表的索引表。 第二表的每个条目包括跳转指针和指示下一访问的第一表的第一表指针。 根据包含在第二表的访问条目中的第一表指针，使用目的地址的对应部分检索所访问的第一表的条目，交替地访问第二表和所选择的第一表。 从第二个表的最终访问的条目读取跳转指针作为检索结果。

公开(公告)号：US5383181A

公开(公告)日：1995-01-17

申请号：US968507

申请日：1992-10-29

申请人： Toshiya Aramaki

发明人： Toshiya Aramaki

IPC分类号： H04L12/54 ,  H04L12/70 ,  H04L12/933 ,  H04L12/937 ,  H04L12/939 ,  H04Q11/04 ,  H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/106 ,  H04L49/1553 ,  H04L49/255 ,  H04L49/552 ,  H04Q11/0478 ,  H04L2012/561 ,  H04L2012/565 ,  H04L49/15 ,  H04L49/254

摘要： In a packet switching system having input ports (20-1-1 to 20-8-8) supplied with input packets and output ports (21-1-1 to 21-8-8) producing output packets, each of time stampers (22-1-1 to 22-8-8) connected to the input ports assigns a time stamp to the input packet supplied thereto to produce a time stamped packet. Connected to the time stampers, each of primary switches (23-1 to 23-8) carries out a primary switching operation on the time stamped packets supplied thereto so as to connect input lines thereof and output lines thereof in one-to-one correspondence to produce primary switched packets. Connected to the primary switches in a cross link connection fashion, each of secondary switches (24-1 to 24-8) carries out a secondary switching operation on the primary switched packets on the basis of destination addresses thereof in sequence to produce secondary switched packets. Connected to the secondary switches in the cross link connection fashion, each of ternary switches (25-1 to 25-8) corrects sequence of the secondary switched packets on the basis of the time stamps assigned thereto to produce sequence corrected packets and then carries out a ternary switching operation on the sequence corrected packets on the basis of the destination addresses thereof to produce ternary switched packets. Each output port produces each ternary switched packet as each output port.

摘要翻译： 在具有提供有输入分组的输入端口（20-1-1至20-8-8）和产生输出分组的输出端口（21-1-1至21-8-8）的分组交换系统中，每个时间戳 22-1-1至22-8-8）向输入端口分配一个时间戳，以产生一个时间戳分组。 连接到时间戳的每个主开关（23-1至23-8）对提供给它的时间戳包进行初次切换操作，以便将其输入线和其输出线一一对应 以产生主交换分组。 以交叉连接方式连接到主交换机，每个辅助交换机（24-1至24-8）依次以其目的地地址对主交换分组进行二次交换操作，以产生二次交换分组 。 以交叉连接方式连接到次级交换机，每个三进制交换机（25-1至25-8）根据分配给它的时间标记来校正二次交换分组的序列，以产生序列校正分组，然后执行 基于其目的地地址对序列校正的分组进行三次切换操作，以产生三进制交换分组。 每个输出端口产生每个三进制交换分组作为每个输出端口。

公开(公告)号：US6055234A

公开(公告)日：2000-04-25

申请号：US870722

申请日：1997-06-06

申请人： Toshiya Aramaki

发明人： Toshiya Aramaki

IPC分类号： H04Q3/00 ,  H04L12/863 ,  H04L12/931 ,  H04L12/933 ,  H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/255 ,  H04L49/309

摘要： In an ATM switching control method, a table is formed to store the relationship between a memory address in a shared cell memory, at which an input cell is stored, and one of available area information indicating that the memory address in the shared cell memory is an available area and cell output information indicating that the memory address in the shared cell memory is an unavailable area. When a cell is to be input, available area information about the shared cell memory is used as a search key to search the table for a memory address in the shared cell memory. The input cell is stored in the shared cell memory in accordance with the searched memory address. Cell output information is stored in the table in accordance with the memory address in the shared cell memory at which the cell is stored. When the cell is to be read out, cell output information is used as a search key to search the table for a memory address in the shared cell memory. The cell is read out from the shared cell memory in accordance with the searched memory address. An ATM switch is also disclosed.

摘要翻译： 在ATM切换控制方法中，形成表以存储存储输入单元的共享单元存储器中的存储器地址与表示共享单元存储器中的存储器地址的可用区域信息之间的关系的表 指示共享单元存储器中的存储器地址是不可用区域的可用区域和单元输出信息。 当要输入单元时，使用关于共享单元存储器的可用区域信息作为搜索键来搜索表中的共享单元存储器中的存储器地址。 输入单元根据搜索的存储器地址存储在共享单元存储器中。 单元输出信息根据存储单元的共享单元存储器中的存储器地址存储在表中。 当要读出单元时，将单元输出信息用作搜索键，以在表中搜索共享单元存储器中的存储器地址。 根据搜索到的存储器地址，从共享单元存储器读出单元。 还公开了ATM交换机。

公开(公告)号：US5483521A

公开(公告)日：1996-01-09

申请号：US280660

申请日：1994-07-28

申请人： Toshiya Aramaki

发明人： Toshiya Aramaki

IPC分类号： H04Q3/00 ,  H04L12/931 ,  H04L12/937 ,  H04Q11/04 ,  H04J3/24

CPC分类号： H04L12/5601 ,  H04L49/107 ,  H04L49/1553 ,  H04Q11/0478 ,  H04L2012/565 ,  H04L2012/5681

摘要： In a cell switching system having a plurality of input ports and a plurality of output ports in which cells of a fixed length packet input from said plurality of input ports are output from the desired output ports in accordance with address information added to each cell, a cell distributing section is provided, corresponding to an input port, to separate input cells at a unit of cell to output them to thus selected output line, an output cell switching section is provided, corresponding to the output line of the cell distributing section, to detect address information added to the cell, and to output to the output line depending on a sequence inputted of cells towards the same output line without replacing such order, and a cell output control section is provided, corresponding to the output port, to perform a cell sequence aligning control.

摘要翻译： 在具有多个输入端口和多个输出端口的单元交换系统中，根据添加到每个单元的地址信息，从所述多个输入端口输入的固定长度分组的单元从期望的输出端口输出， 提供对应于输入端口的单元分配部分，以单元为单位分离输入单元，将它们输出到这样选择的输出线，将与单元分配单元的输出线对应的输出单元切换部分提供给 检测添加到单元的地址信息，并且根据输入的单元向同一输出行输入的顺序输出到输出行而不替换该顺序，并且提供对应于输出端口的单元输出控制部分，以执行 细胞序列对齐控制。

公开(公告)号：US5253251A

公开(公告)日：1993-10-12

申请号：US817893

申请日：1992-01-08

申请人： Toshiya Aramaki

发明人： Toshiya Aramaki

IPC分类号： H04L12/70 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935 ,  H04L12/56

CPC分类号： H04L49/1538 ,  H04L49/1553 ,  H04L49/30 ,  H04L49/3081 ,  H04L2012/565 ,  H04L49/20 ,  H04L49/3009 ,  H04L49/503

摘要： In a fast packet switching system, packet distributors are associated respectively with input ports for receiving successive packets therefrom and attaching a timeslot number to each of the received packets, and uniformly distributing the packets to output terminals of each distributor. Packet switches are provided corresponding in number to the output terminals of each packet distributor. Each packet switch has input terminals corresponding in number to the packet distributors and output terminals corresponding in number to the output ports. The input terminals of each packet switch are coupled to respective output terminals of the distributors for switching a packet from one of its input terminals to one of its output terminals in accordance with a destination address contained in the packet. Packet sequencers are associated respectively with the output ports. Each packet sequencer has input terminals coupled to respective output terminals of the packet switches for examining the timeslot numbers attached to packets from its input terminals and delivering the packets to the associated output port in accordance with the examined timeslot numbers.