公开(公告)号：US08400484B2

公开(公告)日：2013-03-19

申请号：US12964676

申请日：2010-12-09

申请人： Tatsuo Furukawa ,  Nobuyuki Hirayama ,  Ryo Kasai ,  Shinichi Omo ,  Hiroyuki Nakamura ,  Kimiyuki Hayasaki

发明人： Tatsuo Furukawa ,  Nobuyuki Hirayama ,  Ryo Kasai ,  Shinichi Omo ,  Hiroyuki Nakamura ,  Kimiyuki Hayasaki

IPC分类号： B41J2/35 ,  B41J2/005

CPC分类号： B41J2/07 ,  B41J2/04541 ,  B41J2/04546 ,  B41J2/355

摘要： A device includes a first element substrate and a second element substrate for driving a driving element; a first signal input unit connected to an input terminal of the first element substrate; a second signal input unit connected to an input terminal of the second element substrate; and a signal output unit. Each of the first and second element substrates includes a driving element, a first signal generation unit configured to output a first signal, a second signal generation unit configured to output a second signal, an input terminal, an output terminal, and a selection unit configured to receive a signal from the first and the second signal generation units, select one of a state of the first signal, a state of the second signal, and a high-impedance state on the basis of the selection signal input from the input terminal, and output the state to the output terminal.

公开(公告)号：US20110310210A1

公开(公告)日：2011-12-22

申请号：US12964676

申请日：2010-12-09

申请人： Tatsuo Furukawa ,  Nobuyuki Hirayama ,  Ryo Kasai ,  Shinichi Omo ,  Hiroyuki Nakamura ,  Kimiyuki Hayasaki

发明人： Tatsuo Furukawa ,  Nobuyuki Hirayama ,  Ryo Kasai ,  Shinichi Omo ,  Hiroyuki Nakamura ,  Kimiyuki Hayasaki

IPC分类号： B41J2/35

CPC分类号： B41J2/07 ,  B41J2/04541 ,  B41J2/04546 ,  B41J2/355

摘要： A device includes a first element substrate and a second element substrate for driving a driving element; a first signal input unit connected to an input terminal of the first element substrate; a second signal input unit connected to an input terminal of the second element substrate; and a signal output unit. Each of the first and second element substrates includes a driving element, a first signal generation unit configured to output a first signal, a second signal generation unit configured to output a second signal, an input terminal, an output terminal, and a selection unit configured to receive a signal from the first and the second signal generation units, select one of a state of the first signal, a state of the second signal, and a high-impedance state on the basis of the selection signal input from the input terminal, and output the state to the output terminal.

摘要翻译： 一种器件包括用于驱动驱动元件的第一元件基板和第二元件基板; 连接到第一元件基板的输入端的第一信号输入单元; 连接到第二元件基板的输入端的第二信号输入单元; 和信号输出单元。 第一和第二元件基板中的每一个包括驱动元件，被配置为输出第一信号的第一信号生成单元，被配置为输出第二信号的第二信号生成单元，输入端子，输出端子和配置的选择单元 为了从第一和第二信号发生单元接收信号，基于从输入端输入的选择信号选择第一信号的状态，第二信号的状态和高阻抗状态中的一个， 并将该状态输出到输出端子。

公开(公告)号：US20110279511A1

公开(公告)日：2011-11-17

申请号：US12965744

申请日：2010-12-10

申请人： Tomoko Kudo ,  Tatsuo Furukawa ,  Nobuyuki Hirayama ,  Ryo Kasai ,  Kimiyuki Hayasaki

发明人： Tomoko Kudo ,  Tatsuo Furukawa ,  Nobuyuki Hirayama ,  Ryo Kasai ,  Kimiyuki Hayasaki

IPC分类号： B41J29/38 ,  B41J3/407

CPC分类号： B41J2/0458 ,  B41J2/04541 ,  B41J2/0455

摘要： A substrate includes a first and a second element arrays in each of which a plurality of elements is arrayed along a first direction of the substrate, a first and a second pad arrays in which a plurality of pads is arrayed along respective two opposite sides extending along a second direction of the substrate, a reception circuit configured to receive data for driving the elements, a data circuit configured to generate data corresponding to the first and the second element array, respectively based on the received data, a signal generation circuit configured to generate a period signal for determining a drive period of the elements based on the generated data, and an output circuit configured to output information related to the substrate.

摘要翻译： 衬底包括第一和第二元件阵列，每个元件阵列中的多个元件沿着衬底的第一方向排列;第一和第二焊盘阵列，其中多个焊盘沿相应的两个相对侧延伸 基板的第二方向，被配置为接收用于驱动元件的数据的接收电路，数据电路，被配置为基于接收的数据分别生成与第一和第二元件阵列相对应的数据;信号生成电路，被配置为产生 用于基于所生成的数据确定元件的驱动周期的周期信号，以及被配置为输出与该基板有关的信息的输出电路。

公开(公告)号：US08342620B2

公开(公告)日：2013-01-01

申请号：US12965716

申请日：2010-12-10

申请人： Ryo Kasai ,  Nobuyuki Hirayama ,  Tatsuo Furukawa ,  Kimiyuki Hayasaki

发明人： Ryo Kasai ,  Nobuyuki Hirayama ,  Tatsuo Furukawa ,  Kimiyuki Hayasaki

IPC分类号： B41J29/38

CPC分类号： B41J2/04598 ,  B41J2/04541 ,  B41J2/0458 ,  B41J2202/20 ,  B41J2202/21

摘要： According to an aspect of the present invention, a high-resolution, small-size, low-cost driving device includes a clock signal generating unit configured to receive a first clock signal of a differential signaling system and generate a second clock signal, an input unit configured to input a data signal which includes first information and second information, a first timing generating unit configured to select an edge of the second clock signal based on the first information and to generate a first signal by counting occurrences of the selected edge a second timing generating unit configured to select edge of the second clock signal based on the second information and to generate a second signal by counting occurrences of the selected edge, a logical circuit configured to generate a pulse signal based on the first and second signals, and a driving element configured to drive a driven element using the pulse signal.

摘要翻译： 根据本发明的一个方面，高分辨率，小尺寸，低成本的驱动装置包括时钟信号产生单元，其被配置为接收差分信号系统的第一时钟信号并产生第二时钟信号，输入 被配置为输入包括第一信息和第二信息的数据信号的单元，第一定时生成单元，被配置为基于第一信息来选择第二时钟信号的边沿，并且通过对所选择的边缘的出现进行计数来生成第一信号，第二信号 定时生成单元，被配置为基于所述第二信息选择所述第二时钟信号的边缘，并且通过对所选择的边缘的出现进行计数来生成第二信号;逻辑电路，被配置为基于所述第一和第二信号生成脉冲信号;以及 驱动元件，被配置为使用所述脉冲信号驱动从动元件。

公开(公告)号：US09579888B2

公开(公告)日：2017-02-28

申请号：US12965744

申请日：2010-12-10

申请人： Tomoko Kudo ,  Tatsuo Furukawa ,  Nobuyuki Hirayama ,  Ryo Kasai ,  Kimiyuki Hayasaki

发明人： Tomoko Kudo ,  Tatsuo Furukawa ,  Nobuyuki Hirayama ,  Ryo Kasai ,  Kimiyuki Hayasaki

IPC分类号： B41J2/05 ,  B41J2/045

CPC分类号： B41J2/0458 ,  B41J2/04541 ,  B41J2/0455

摘要： A substrate includes a first and a second element arrays in each of which a plurality of elements is arrayed along a first direction of the substrate, a first and a second pad arrays in which a plurality of pads is arrayed along respective two opposite sides extending along a second direction of the substrate, a reception circuit configured to receive data for driving the elements, a data circuit configured to generate data corresponding to the first and the second element array, respectively based on the received data, a signal generation circuit configured to generate a period signal for determining a drive period of the elements based on the generated data, and an output circuit configured to output information related to the substrate.

摘要翻译： 衬底包括第一和第二元件阵列，每个元件阵列中的多个元件沿着衬底的第一方向排列;第一和第二焊盘阵列，其中多个焊盘沿相应的两个相对侧延伸 基板的第二方向，被配置为接收用于驱动元件的数据的接收电路，数据电路，被配置为基于接收的数据分别生成与第一和第二元件阵列相对应的数据;信号生成电路，被配置为产生 用于基于所生成的数据确定元件的驱动周期的周期信号，以及被配置为输出与该基板有关的信息的输出电路。

公开(公告)号：US20110274213A1

公开(公告)日：2011-11-10

申请号：US12964667

申请日：2010-12-09

申请人： Ryo Kasai ,  Nobuyuki Hirayama ,  Tatsuo Furukawa ,  Kimiyuki Hayasaki ,  Hisao Terajima

发明人： Ryo Kasai ,  Nobuyuki Hirayama ,  Tatsuo Furukawa ,  Kimiyuki Hayasaki ,  Hisao Terajima

IPC分类号： H04L27/00

CPC分类号： B41J2/07 ,  G06F2213/0038 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/49

摘要： Data transfer is realized to support a high-speed and complex driving control of the driving element. A driving device includes a driving unit configured to supply a driving element with a pulse signal that determines a driving period to drive the driving element, an input unit configured to receive, in synchronization with a trigger signal, a data signal containing first information, second information, a first flag and a second flag that determine a waveform of the pulse signal, a first setting unit configured to set in the driving unit the first information that is input to the input unit, a retaining unit configured to read and retain the second information on the basis of the first flag, and a second setting unit configured to set in the driving unit the second information that is retained in the retaining unit on the basis of the second flag.

摘要翻译： 实现数据传输以支持驱动元件的高速和复杂的驱动控制。 驱动装置包括：驱动单元，被配置为向驱动元件提供确定用于驱动驱动元件的驱动周期的脉冲信号;输入单元，被配置为与触发信号同步地接收包含第一信息的数据信号，第二信号 信息，第一标志和第二标志，确定脉冲信号的波形;第一设置单元，被配置为在驱动单元中设置输入到输入单元的第一信息;保持单元，被配置为读取并保持第二信号 基于第一标志的信息，以及第二设定单元，被配置为基于第二标志将驱动单元中保留在保持单元中的第二信息设置在驱动单元中。

公开(公告)号：US08864276B2

公开(公告)日：2014-10-21

申请号：US12963661

申请日：2010-12-09

申请人： Hidenori Yamato ,  Tatsuo Furukawa ,  Nobuyuki Hirayama ,  Ryo Kasai ,  Kimiyuki Hayasaki ,  Shinji Takagi

发明人： Hidenori Yamato ,  Tatsuo Furukawa ,  Nobuyuki Hirayama ,  Ryo Kasai ,  Kimiyuki Hayasaki ,  Shinji Takagi

IPC分类号： B41J29/393 ,  B41J2/045

CPC分类号： B41J2/04508 ,  B41J2/0451 ,  B41J2/04541 ,  B41J2/04543 ,  B41J2/0458 ,  B41J2202/20

摘要： This invention is directed to real time detection of occurrence of a transfer error and feedback of the detection result to a printing apparatus in consideration of a possible risk that a signal transfer error occurs on a transfer path that becomes longer as the printhead is elongated. To accomplish this, in a printhead configured by cascade-connecting a plurality of element substrates, information of a transfer error detected in real time in each element substrate during transfer of a print data signal is output to an element substrate on the next stage by taking account of information input from an element substrate on the preceding stage. Information containing pieces of information from all element substrates is output from an element substrate on the final stage.

摘要翻译： 考虑到在打印头长度变长的传送路径上发生信号传递错误的可能风险，本发明涉及实时检测传送错误的发生和检测结果的反馈。 为了实现这一点，在通过级联连接多个元件基板的打印头中，在打印数据信号的传送期间在每个元件基板中实时检测到的传送错误的信息通过采取以下方式输出到下一级的元件基板 说明从前一阶段的元件基板输入的信息。 从最终级的元件基板输出包含来自所有元件基板的信息的信息。

公开(公告)号：US20110273507A1

公开(公告)日：2011-11-10

申请号：US12963661

申请日：2010-12-09

申请人： Hidenori Yamato ,  Tatsuo Furukawa ,  Nobuyuki Hirayama ,  Ryo Kasai ,  Kimiyuki Hayasaki ,  Shinji Takagi

发明人： Hidenori Yamato ,  Tatsuo Furukawa ,  Nobuyuki Hirayama ,  Ryo Kasai ,  Kimiyuki Hayasaki ,  Shinji Takagi

IPC分类号： B41J29/393

CPC分类号： B41J2/04508 ,  B41J2/0451 ,  B41J2/04541 ,  B41J2/04543 ,  B41J2/0458 ,  B41J2202/20

摘要： This invention is directed to real time detection of occurrence of a transfer error and feedback of the detection result to a printing apparatus in consideration of a possible risk that a signal transfer error occurs on a transfer path that becomes longer as the printhead is elongated. To accomplish this, in a printhead configured by cascade-connecting a plurality of element substrates, information of a transfer error detected in real time in each element substrate during transfer of a print data signal is output to an element substrate on the next stage by taking account of information input from an element substrate on the preceding stage. Information containing pieces of information from all element substrates is output from an element substrate on the final stage.

摘要翻译： 考虑到在打印头长度变长的传送路径上发生信号传递错误的可能风险，本发明涉及实时检测传送错误的发生和检测结果的反馈。 为了实现这一点，在通过级联连接多个元件基板的打印头中，在打印数据信号的传送期间在每个元件基板中实时检测到的传送错误的信息通过采取以下方式输出到下一级的元件基板 说明从前一阶段的元件基板输入的信息。 从最终级的元件基板输出包含来自所有元件基板的信息的信息。

公开(公告)号：US20110273498A1

公开(公告)日：2011-11-10

申请号：US12965716

申请日：2010-12-10

申请人： Ryo Kasai ,  Nobuyuki Hirayama ,  Tatsuo Furukawa ,  Kimiyuki Hayasaki

发明人： Ryo Kasai ,  Nobuyuki Hirayama ,  Tatsuo Furukawa ,  Kimiyuki Hayasaki

IPC分类号： B41J29/38 ,  H03K3/00

CPC分类号： B41J2/04598 ,  B41J2/04541 ,  B41J2/0458 ,  B41J2202/20 ,  B41J2202/21

摘要： According to an aspect of the present invention, a high-resolution, small-size, low-cost driving device includes a clock signal generating unit configured to receive a first clock signal of a differential signaling system and generate a second clock signal, an input unit configured to input a data signal which includes first information and second information, a first timing generating unit configured to select an edge of the second clock signal based on the first information and to generate a first signal by counting occurrences of the selected edge a second timing generating unit configured to select edge of the second clock signal based on the second information and to generate a second signal by counting occurrences of the selected edge, a logical circuit configured to generate a pulse signal based on the first and second signals, and a driving element configured to drive a driven element using the pulse signal.

摘要翻译： 根据本发明的一个方面，高分辨率，小尺寸，低成本的驱动装置包括时钟信号产生单元，其被配置为接收差分信号系统的第一时钟信号并产生第二时钟信号，输入 被配置为输入包括第一信息和第二信息的数据信号的单元，第一定时生成单元，被配置为基于第一信息来选择第二时钟信号的边沿，并且通过对所选择的边缘的出现进行计数来生成第一信号，第二信号 定时生成单元，被配置为基于所述第二信息选择所述第二时钟信号的边缘，并且通过对所选择的边缘的出现进行计数来生成第二信号;逻辑电路，被配置为基于所述第一和第二信号生成脉冲信号;以及 驱动元件，被配置为使用所述脉冲信号驱动从动元件。

公开(公告)号：US08579399B2

公开(公告)日：2013-11-12

申请号：US12964667

申请日：2010-12-09

申请人： Ryo Kasai ,  Nobuyuki Hirayama ,  Tatsuo Furukawa ,  Kimiyuki Hayasaki ,  Hisao Terajima

发明人： Ryo Kasai ,  Nobuyuki Hirayama ,  Tatsuo Furukawa ,  Kimiyuki Hayasaki ,  Hisao Terajima

IPC分类号： B41J29/38

CPC分类号： B41J2/07 ,  G06F2213/0038 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/49

摘要： Data transfer is realized to support a high-speed and complex driving control of the driving element. A driving device includes a driving unit configured to supply a driving element with a pulse signal that determines a driving period to drive the driving element, an input unit configured to receive, in synchronization with a trigger signal, a data signal containing first information, second information, a first flag and a second flag that determine a waveform of the pulse signal, a first setting unit configured to set in the driving unit the first information that is input to the input unit, a retaining unit configured to read and retain the second information on the basis of the first flag, and a second setting unit configured to set in the driving unit the second information that is retained in the retaining unit on the basis of the second flag.