公开(公告)号：US20120049958A1

公开(公告)日：2012-03-01

申请号：US13221310

申请日：2011-08-30

申请人： Tatsuya TAKEI

发明人： Tatsuya TAKEI

IPC分类号： H03F3/45

CPC分类号： H03F3/45197 ,  H03F3/45201 ,  H03F2203/45082 ,  H03F2203/45352

摘要： An amplifier circuit may include an input differential pair that includes a first transistor and a second transistor, a positive input voltage being supplied to a gate terminal of the first transistor, a negative input voltage being supplied to a gate terminal of the second transistor, a first resistor that generates a differential current corresponding to a differential voltage between the positive input voltage and the negative input voltage, an output differential pair that includes a third transistor and a fourth transistor, a negative output voltage being supplied from a drain terminal of the third terminal, a positive output voltage being supplied from a drain terminal of the fourth terminal, a second resistor that is connected to a reference voltage, the differential current generated by the first resistor being supplied to the second resistor, and a bias circuit that supplies a constant bias current to the first, second, third, and fourth transistors.

摘要翻译： 放大器电路可以包括输入差分对，其包括第一晶体管和第二晶体管，正输入电压被提供给第一晶体管的栅极端，负输入电压被提供给第二晶体管的栅极端， 第一电阻器，其产生对应于正输入电压和负输入电压之间的差分电压的差分电流;包括第三晶体管和第四晶体管的输出差分对，从第三晶体管的漏极端子提供的负输出电压 端子，从第四端子的漏极端子提供的正输出电压，连接到参考电压的第二电阻器，由第一电阻器产生的差分电流被提供给第二电阻器;以及偏置电路， 到第一，第二，第三和第四晶体管的恒定偏置电流。

公开(公告)号：US20090201419A1

公开(公告)日：2009-08-13

申请号：US12350499

申请日：2009-01-08

申请人： Tatsuya TAKEI

发明人： Tatsuya TAKEI

IPC分类号： H04N5/04

CPC分类号： H04N5/378

摘要： A signal processing apparatus includes an analog signal outputting circuit configured to output an analog signal divided into blocks in synchronization with a clock. An operation circuit is configured to operate in a clamping state to hold a reference signal and in a signal outputting state to output an effective signal by performing a specific operation on the analog signal with respect to the reference signal. A control circuit is configured to control the operation circuit and causes the operation circuit to operate in the clamping state longer than a period in which one block of the analog signal is output while the operation circuit remains in the signal outputting state.

摘要翻译： 信号处理装置包括：模拟信号输出电路，被配置为与时钟同步地输出被划分成块的模拟信号。 操作电路被配置为在钳位状态下操作以保持参考信号并且在信号输出状态下通过相对于参考信号对模拟信号执行特定操作来输出有效信号。 控制电路被配置为控制操作电路，并且使得操作电路在钳位状态下比在操作电路保持在信号输出状态期间输出一个模拟信号块的时间段更长时间工作。