公开(公告)号：US12067395B2

公开(公告)日：2024-08-20

申请号：US18098068

申请日：2023-01-17

Applicant: Tenstorrent Inc.

Inventor： Miles Robert Dooley ,  Milos Trajkovic ,  Rakesh Shaji Lal ,  Stanislav Sokorac

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3004 ,  G06F9/30134

Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes a memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.

公开(公告)号：US11599358B1

公开(公告)日：2023-03-07

申请号：US17401005

申请日：2021-08-12

Applicant: Tenstorrent Inc.

Inventor： Miles Robert Dooley ,  Milos Trajkovic ,  Rakesh Shaji Lal ,  Stanislav Sokorac

IPC: G06F9/30 ,  G06F13/36

Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the instruction memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.

公开(公告)号：US20230153110A1

公开(公告)日：2023-05-18

申请号：US18098068

申请日：2023-01-17

Applicant: Tenstorrent Inc.

Inventor： Miles Robert Dooley ,  Milos Trajkovic ,  Rakesh Shaji Lal ,  Stanislav Sokorac

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30134 ,  G06F9/3004

Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes a memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.

公开(公告)号：US20230051122A1

公开(公告)日：2023-02-16

申请号：US17401005

申请日：2021-08-12

Applicant: Tenstorrent Inc.

Inventor： Miles Robert Dooley ,  Milos Trajkovic ,  Rakesh Shaji Lal ,  Stanislav Sokorac

IPC: G06F9/30 ,  G06F13/36

Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the instruction memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.

公开(公告)号：US11567764B1

公开(公告)日：2023-01-31

申请号：US17401005

申请日：2021-08-12

Applicant: Tenstorrent Inc.

Inventor： Miles Robert Dooley ,  Milos Trajkovic ,  Rakesh Shaji Lal ,  Stanislav Sokorac

IPC: G06F9/30 ,  G06F13/36

Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the instruction memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.