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公开(公告)号：US12118060B2
公开(公告)日：2024-10-15
申请号：US17545860
申请日：2021-12-08
申请人： Tenstorrent Inc.
发明人： Davor Capalija , Ljubisa Bajic , Alex Cejkov
IPC分类号： G06F17/16 , G11C11/419
CPC分类号： G06F17/16 , G11C11/419
摘要： Methods and systems relating to computational circuitry are disclosed herein. A disclosed computational circuit includes a math circuit, a first accumulator, and a second accumulator. The first accumulator has a first memory. The second accumulator has a second memory. The first accumulator is communicatively connected to the math circuit and accumulates values from the math circuit in the first memory. The second accumulator is communicatively connected to the first memory and accumulates values from the first memory in the second memory. The first memory is faster and smaller than the second memory.
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公开(公告)号：US12019546B2
公开(公告)日：2024-06-25
申请号：US17982467
申请日：2022-11-07
申请人： Tenstorrent Inc.
发明人： Ljubisa Bajic , Davor Capalija , Ivan Matosevic , Alex Cejkov
IPC分类号： G06F12/0811 , G06F11/34 , G06F12/06 , G06F12/0813 , G06F13/16 , G06N3/063
CPC分类号： G06F12/0811 , G06F11/3466 , G06F12/0646 , G06F12/0813 , G06F13/1668 , G06N3/063
摘要： Methods and systems associated with caches are disclosed. One disclosed system includes at least one memory storing at least two data structures. The at least two data structures include a first data structure and a second data structure. The system also includes at least two caches with a first cache which caches the first data structure and a second cache which caches the second data structure. The system also includes a controller communicatively coupled to the at least two caches. The controller separately configures the first cache based on the first data structure and the second cache based on the second data structure. The system also comprises at least one processor communicatively coupled to the at least two caches. The processor accesses each of the at least two data structures using the at least two caches and during the execution of a complex computation.
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公开(公告)号：US11829752B2
公开(公告)日：2023-11-28
申请号：US17686003
申请日：2022-03-03
申请人： Tenstorrent Inc.
摘要： Processor cores using packet identifiers for routing and computation are disclosed. One method includes executing a complex computation using a set of processing cores. The method includes routing a set of packets using a set of packet identifiers and executing a set of instructions. The set of instructions are defined using a set of operand identifiers. The operand identifiers represent packet identifiers in the set of packet identifiers. In specific implementations the set of the operand identifiers represent packet identifiers in the set of packet identifiers in that a set of memories on the set of processing cores stores data values in common association with both the set of packets, and a set of operands identified by the set of operand identifiers. In specific implementations the set of operand identifiers and packet identifiers are unambiguously mapped to an underlying set of application datums of the complex computation.
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公开(公告)号：US20230281155A1
公开(公告)日：2023-09-07
申请号：US18196418
申请日：2023-05-11
申请人： Tenstorrent Inc.
发明人： Ivan Matosevic , Davor Capalija , Jasmina Vasiljevic , Utku Aydonat , S. Alexander Chin , Djordje Maksimovic , Ljubisa Bajic
IPC分类号： G06F15/78 , G06F15/82 , G06F15/173
CPC分类号： G06F15/7871 , G06F15/7825 , G06F15/825 , G06F15/173 , G06F9/3004
摘要： Methods and systems for executing an application data flow graph on a set of computational nodes are disclosed. The computational nodes can each include a programmable controller from a set of programmable controllers, a memory from a set of memories, a network interface unit from a set of network interface units, and an endpoint from a set of endpoints. A disclosed method comprises configuring the programmable controllers with instructions. The method also comprises independently and asynchronously executing the instructions using the set of programmable controllers in response to a set of events exchanged between the programmable controllers themselves, between the programmable controllers and the network interface units, and between the programmable controllers and the set of endpoints. The method also comprises transitioning data in the set of memories on the computational nodes in accordance with the application data flow graph and in response to the execution of the instructions.
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公开(公告)号：US11709662B2
公开(公告)日：2023-07-25
申请号：US17519947
申请日：2021-11-05
申请人： Tenstorrent Inc.
发明人： Ljubisa Bajic , Davor Capalija , Yu Ting Chen , Andrew Grebenisan , Hassan Farooq , Akhmed Rakhmati , Stephen Chin , Vladimir Blagojevic , Almeet Bhullar , Jasmina Vasiljevic
CPC分类号： G06F9/3838 , G06F8/443 , G06F8/451 , G06F8/453 , G06N3/04
摘要： Methods and systems relating to the field of parallel computing are disclosed herein. The methods and systems disclosed include approaches for sparsity uniformity enforcement for a set of computational nodes which are used to execute a complex computation. A disclosed method includes determining a sparsity distribution in a set of operand data, and generating, using a compiler, a set of instructions for executing, using the set of operand data and a set of processing cores, a complex computation. Alternatively, the method includes altering the operand data. The method also includes distributing the set of operand data to the set of processing cores for use in executing the complex computation in accordance with the set of instructions. Either the altering is conducted to, or the compiler is programmed to, balance the sparsity distribution among the set of processing cores.
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公开(公告)号：US20220188106A1
公开(公告)日：2022-06-16
申请号：US17686003
申请日：2022-03-03
申请人： Tenstorrent Inc.
摘要： Processor cores using packet identifiers for routing and computation are disclosed. One method includes executing a complex computation using a set of processing cores. The method includes routing a set of packets using a set of packet identifiers and executing a set of instructions. The set of instructions are defined using a set of operand identifiers. The operand identifiers represent packet identifiers in the set of packet identifiers. In specific implementations the set of the operand identifiers represent packet identifiers in the set of packet identifiers in that a set of memories on the set of processing cores stores data values in common association with both the set of packets, and a set of operands identified by the set of operand identifiers. In specific implementations the set of operand identifiers and packet identifiers are unambiguously mapped to an underlying set of application datums of the complex computation.
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公开(公告)号：US20200174799A1
公开(公告)日：2020-06-04
申请号：US16788069
申请日：2020-02-11
申请人： Tenstorrent Inc.
发明人： Ljubisa Bajic , Milos Trajkovic , Ivan Hamer , Syed Gilani
摘要： Processing cores with the ability to suppress operations based on a contribution estimate for those operation for purposes of increasing the overall performance of the core are disclosed. Associated methods that can be conducted by such processing cores are also disclosed. One such method includes generating a reference value for a composite computation. A complete execution of the composite computation generates a precise output and requires execution of a set of component computations. The method also includes generating a component computation approximation. The method also includes evaluating the component computation approximation with the reference value. The method also includes executing a partial execution of the composite computation using the component computation approximation to produce an estimated output. The method also includes suppressing the component computation, while executing the partial execution, based on the evaluation of the component computation approximation with the reference value.
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公开(公告)号：US20190272183A1
公开(公告)日：2019-09-05
申请号：US16416749
申请日：2019-05-20
申请人： Tenstorrent Inc.
发明人： Ljubisa Bajic , Milos Trajkovic , Ivan Hamer , Syed Gilani
摘要： Processing cores with the ability to suppress operations based on a contribution estimate for those operation for purposes of increasing the overall performance of the core are disclosed. Associated methods that can be conducted by such processing cores are also disclosed. One such method includes generating a reference value for a composite computation. A complete execution of the composite computation generates a precise output and requires execution of a set of component computations. The method also includes generating a component computation approximation. The method also includes evaluating the component computation approximation with the reference value. The method also includes executing a partial execution of the composite computation using the component computation approximation to produce an estimated output. The method also includes suppressing the component computation, while executing the partial execution, based on the evaluation of the component computation approximation with the reference value.
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公开(公告)号：US10318317B2
公开(公告)日：2019-06-11
申请号：US15975930
申请日：2018-05-10
申请人： Tenstorrent Inc.
发明人： Ljubisa Bajic , Milos Trajkovic , Ivan Hamer , Syed Gilani
摘要： Processing cores with the ability to suppress operations based on a contribution estimate for those operation for purposes of increasing the overall performance of the core are disclosed. Associated methods that can be conducted by such processing cores are also disclosed. One such method includes generating a reference value for a composite computation. A complete execution of the composite computation generates a precise output and requires execution of a set of component computations. The method also includes generating a component computation approximation. The method also includes evaluating the component computation approximation with the reference value. The method also includes executing a partial execution of the composite computation using the component computation approximation to produce an estimated output. The method also includes suppressing the component computation, while executing the partial execution, based on the evaluation of the component computation approximation with the reference value.
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公开(公告)号：US20240345840A1
公开(公告)日：2024-10-17
申请号：US18756494
申请日：2024-06-27
申请人： Tenstorrent Inc.
发明人： Ljubisa Bajic , Milos Trajkovic , Ivan Hamer
CPC分类号： G06F9/30072 , G06F9/3001 , G06F9/4494 , G06N3/04 , G06N3/045 , G06N3/063 , G06N3/08
摘要： A processing core for the efficient execution of a directed graph is disclosed. The processing core includes a memory and a first and a second data tile stored in the memory. The first and second data tiles include a first and a second set of data elements stored contiguously in the memory. The processing core also includes metadata relationally stored with the first data tile in the memory. The processing core also includes an execution engine, a control unit, and an instruction. Execution of the instruction uses the execution engine, a first data element in the first set of data elements, and a second data element in the second set of data elements. The control unit conditions execution of the instruction using the metadata. A standard execution of the instruction generates a standard output. A conditional execution of the instruction operation generates a conditionally executed output.
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