公开(公告)号：US06198679B1

公开(公告)日：2001-03-06

申请号：US09408717

申请日：1999-09-29

申请人： Teruhiko Nakasu ,  Shigeki Tomishima ,  Tsukasa Ooishi

发明人： Teruhiko Nakasu ,  Shigeki Tomishima ,  Tsukasa Ooishi

IPC分类号： G11C700

CPC分类号： G11C7/1072 ,  G11C7/22

摘要： The objective of the invention is to read and write data in synchronization with a high-speed clock signal. The pulse width of the timing control signal (FY signal), which determines the pulse width of the column select signal (YS signal), is enlarged in a data read operation and reduced in a data write operation. In this way, the activation pulse width of the column select signal is enlarged in a data read operation and reduced in a data write operation. Consequently, in a data read operation, the time for connecting a bit line pair to an input/output line pair becomes longer. The potential difference of the bit line pair can be completely transferred to the input/output line pair. Therefore, data can be read correctly in synchronization with a high-speed clock signal.

摘要翻译： 本发明的目标是与高速时钟信号同步地读取和写入数据。 在数据读取操作中放大确定列选择信号（YS信号）的脉冲宽度的定时控制信号（FY信号）的脉冲宽度，并在数据写入操作中减小。 以这种方式，列选择信号的激活脉冲宽度在数据读取操作中被放大并且在数据写入操作中被减少。 因此，在数据读取操作中，将位线对连接到输入/输出线对的时间变长。 位线对的电位差可以完全传输到输入/输出线对。 因此，可以与高速时钟信号同步读取数据。