公开(公告)号：US20240311159A1

公开(公告)日：2024-09-19

申请号：US18670932

申请日：2024-05-22

Applicant: Texas Instruments Incorporated

Inventor： ALAN DAVIS ,  VENKATESH NATARAJAN ,  ALEXANDER TESSAROLO

IPC: G06F9/38 ,  G06F7/02

CPC classification number: G06F9/3869 ,  G06F7/02

Abstract: A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

公开(公告)号：US20240111541A1

公开(公告)日：2024-04-04

申请号：US17958219

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： ALAN DAVIS ,  VENKATESH NATARAJAN ,  ALEXANDER TESSAROLO

IPC: G06F9/38 ,  G06F7/02

CPC classification number: G06F9/3869 ,  G06F7/02

Abstract: A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.