公开(公告)号：US20240111541A1

公开(公告)日：2024-04-04

申请号：US17958219

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： ALAN DAVIS ,  VENKATESH NATARAJAN ,  ALEXANDER TESSAROLO

IPC: G06F9/38 ,  G06F7/02

CPC classification number: G06F9/3869 ,  G06F7/02

Abstract: A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

公开(公告)号：US20240311159A1

公开(公告)日：2024-09-19

申请号：US18670932

申请日：2024-05-22

Applicant: Texas Instruments Incorporated

Inventor： ALAN DAVIS ,  VENKATESH NATARAJAN ,  ALEXANDER TESSAROLO

IPC: G06F9/38 ,  G06F7/02

CPC classification number: G06F9/3869 ,  G06F7/02

Abstract: A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

公开(公告)号：US20250021656A1

公开(公告)日：2025-01-16

申请号：US18771795

申请日：2024-07-12

Applicant: Texas Instruments Incorporated

Inventor： David Foley ,  Saya Goud Langadi ,  ALEXANDER TESSAROLO ,  Venkatesh Natarajan

IPC: G06F21/57 ,  G06F21/54 ,  G06F21/60

Abstract: In described examples, a circuit device includes a memory having a set of memory ranges, a logic circuit, access protection registers (APRs), ZONE debug permission registers, and a processor coupled to the memory. Each APR stores memory access permissions for an associated memory range. Each ZONE debug permission register stores debug permissions for a ZONE. Each ZONE is associated with a subset of the APRs so that each APR is associated with one ZONE. The processor executes a debug instruction to control the circuit device as follows. An APR associated with a memory address in the debug instruction provides a first permission to a first logic circuit input. The ZONE debug permission registers provide a second permission responsive to a credential to a second logic circuit input. The processor performs a debug action responsive to the debug instruction and a logic circuit output.

公开(公告)号：US20250021494A1

公开(公告)日：2025-01-16

申请号：US18771733

申请日：2024-07-12

Applicant: Texas Instruments Incorporated

Inventor： David Foley ,  Saya Goud Langadi ,  ALEXANDER TESSAROLO ,  Venkatesh Natarajan

IPC: G06F12/14 ,  G06F9/38

Abstract: In described examples, a circuit device includes a memory having a set of memory ranges and a processor device coupled to the memory. The processor device is configured to fetch programmable instructions from the memory, and configured to determine memory access and execution permissions for the programmable instructions. Permissions are determined responsive to a set of a set of access protection registers (APRs) and a set of LINKs. The APRs each specify permissions for a respective associated memory range. The LINKs are each associated with a respective subset of the APRs. Each of the APRs specifies access protection responsive to each LINK. Each of the programmable instructions corresponds to the APR (source APR) associated with a memory range in which the programmable instruction is stored, and corresponds to the LINK (source LINK) associated with the respective source APR.