公开(公告)号：US08748976B1

公开(公告)日：2014-06-10

申请号：US13787044

申请日：2013-03-06

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  John Manning Savidge Neilson ,  Simon John Molloy ,  Hideaki Kawahara ,  Hong Yang ,  Seetharaman Sridhar ,  Hao Wu ,  Boling Wen

IPC: H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0649 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802

Abstract: A semiconductor device contains a vertical MOS transistor with instances of a vertical RESURF trench on opposite sides of a vertical drift region. The vertical RESURF trench contains a dielectric trench liner on sidewalls, and a lower field plate and an upper field plate above the lower field plate. The dielectric trench liner between the lower field plate and the vertical drift region is thicker than between the upper field plate and the vertical drift region. A gate is disposed over the vertical drift region and is separate from the upper field plate. The upper field plate and the lower field plate are electrically coupled to a source electrode of the vertical MOS transistor.

Abstract translation: 半导体器件包含垂直MOS晶体管，其具有在垂直漂移区域的相对侧上的垂直RESURF沟槽的实例。 垂直RESURF沟槽包含侧壁上的电介质沟槽衬垫，下场板上的下场板和上场板。 下场板和垂直漂移区之间的电介质沟槽衬垫比上场板和垂直漂移区之间厚。 栅极设置在垂直漂移区上方并与上场板分离。 上场板和下场板电耦合到垂直MOS晶体管的源电极。