公开(公告)号：US09691751B2

公开(公告)日：2017-06-27

申请号：US14570530

申请日：2014-12-15

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar Srinivasan ,  Khanh Quang Le ,  Collin White ,  Sopa Chevacharoenkul ,  Ashley Norris ,  Bernard John Fischer

IPC: H01L27/02 ,  H01L21/763 ,  H01L29/06

CPC classification number: H01L27/0248 ,  H01L21/763 ,  H01L21/823878 ,  H01L29/0649

Abstract: A method of fabricating an integrated circuit (IC) includes etching a trench in a semiconductor substrate having an aspect ratio (AR) ≧5 and a trench depth ≧10 μm. A dielectric liner is formed along the walls of the trench to form a dielectric lined trench. In-situ doped polysilicon is deposited into the trench to form a dielectric lined polysilicon filled trench having a doped polysilicon filler therein. The doped polysilicon filler after completion of fabricating the IC is essentially polysilicon void-free and has a 25° C. sheet resistance ≦100 ohms/sq. The method can include etching an opening at a bottom of the dielectric liner before depositing the polysilicon to provide ohmic contact to the semiconductor substrate.