Read-current and word line delay path tracking for sense amplifier enable timing
    1.
    发明授权
    Read-current and word line delay path tracking for sense amplifier enable timing 有权
    读取电流和字线延迟路径跟踪,用于读出放大器使能定时

    公开(公告)号:US09576621B2

    公开(公告)日:2017-02-21

    申请号:US13898803

    申请日:2013-05-21

    CPC classification number: G11C7/12 G11C7/08 G11C7/227 G11C8/08

    Abstract: A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal.

    Abstract translation: 集成电路中的静态随机存取存储器(SRAM),其具有用于定时使能读出放大器的电路。 存储器包括读/写SRAM单元以及排列在读/写单元侧的一行或多行的字线跟踪晶体以及沿着读/写单元的一侧排列在列中的读取 - 跟踪晶体管 。 参考字线延伸在字线跟踪晶体管上,其远端与驱动器连接,以在读取跟踪晶体管中传递晶体管。 读取跟踪晶体管被预设为已知数据状态,当响应于参考字线访问时,放电参考位线,该参考位线又驱动读出放大器使能信号。

    Read-Current and Word Line Delay Path Tracking for Sense Amplifier Enable Timing
    2.
    发明申请
    Read-Current and Word Line Delay Path Tracking for Sense Amplifier Enable Timing 有权
    读取电流和字线延迟路径跟踪,用于检测放大器启用定时

    公开(公告)号:US20140010032A1

    公开(公告)日:2014-01-09

    申请号:US13898803

    申请日:2013-05-21

    CPC classification number: G11C7/12 G11C7/08 G11C7/227 G11C8/08

    Abstract: A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal.

    Abstract translation: 集成电路中的静态随机存取存储器(SRAM),其具有用于定时使能读出放大器的电路。 存储器包括读/写SRAM单元以及排列在读/写单元侧的一行或多行的字线跟踪晶体以及沿着读/写单元的一侧排列在列中的读取 - 跟踪晶体管 。 参考字线延伸在字线跟踪晶体管上,其远端与驱动器连接,以在读取跟踪晶体管中传递晶体管。 读取跟踪晶体管被预设为已知数据状态,当响应于参考字线访问时,放电参考位线,该参考位线又驱动读出放大器使能信号。

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