公开(公告)号：US20240290641A1

公开(公告)日：2024-08-29

申请号：US18175718

申请日：2023-02-28

Applicant: Texas Instruments Incorporated

Inventor： Hao Yang ,  John K. Arch

IPC: H01L21/67 ,  H01L29/06

CPC classification number: H01L21/67259 ,  H01L29/0649

Abstract: A method includes performing a fabrication process that fabricates a wafer having an upper region and unit areas arranged in rows along a first direction and columns along an orthogonal second direction and respective scribe streets between adjacent unit areas to: form first and second electrical components on or in the upper region in respective unit areas or scribe streets, the first and second electrical components spaced apart from one another and including structural features with different respective first and second spacing distances along the first direction.

公开(公告)号：US20240038580A1

公开(公告)日：2024-02-01

申请号：US17877976

申请日：2022-07-31

Applicant: Texas Instruments Incorporated

Inventor： Hao Yang ,  Asad Haider ,  Guruvayurappan Mathur ,  Abbas Ali ,  Alexei Sadovnikov ,  Umamaheswari Aghoram

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L29/0623

Abstract: An electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, the semiconductor surface layer over the semiconductor substrate and having a top surface, a buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, a dielectric isolation layer that extends over and into the semiconductor surface layer, a deep trench structure that extends through the dielectric isolation layer into the semiconductor surface layer, and a silicide blocking layer on a top surface of the deep trench structure.

公开(公告)号：US20240038579A1

公开(公告)日：2024-02-01

申请号：US17877964

申请日：2022-07-31

Applicant: Texas Instruments Incorporated

Inventor： Asad Haider ,  Hao Yang ,  Guruvayurappan Mathur ,  Alexei Sadovnikov ,  Abbas Ali ,  Umamaheswari Aghoram

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L29/0623

Abstract: An electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, as well as a buried layer, a deep trench structure and a shallow trench isolation structure, the semiconductor surface layer over the semiconductor substrate and having a top surface, the buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, the deep trench structure including a trench that extends through the semiconductor surface layer and into the buried layer, a dielectric liner on a sidewall of the trench from the semiconductor surface layer to the buried layer, and polysilicon that extends on the dielectric liner and fills the trench to the side of the semiconductor surface layer, the shallow trench isolation structure extends into the semiconductor surface layer, and the shallow trench isolation structure in contact with the deep trench structure.