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公开(公告)号：US20240364276A1
公开(公告)日：2024-10-31
申请号：US18648037
申请日：2024-04-26
Applicant: Texas Instruments Incorporated
Inventor： Chandrasekhar Sriram , Sarma Sundareswara Gunturi , Jawaharlal Tangudu , Harshit Moondra , Harsh Garg , Sanjay Pennam
CPC classification number: H03F1/3241 , H03F3/245 , H03F2200/451
Abstract: Methods, apparatus, systems, and articles of manufacture are described for dynamic digital pre-distortion correction. An example system includes programmable circuitry operable to execute computer readable instructions to at least: generate signal statistics based on an input signal; group the signal statistics into a first group of signal statistics or a second group of signal statistics based on time constants of the signal statistics; decimate the first group of signal statistics; generate a first predistortion term based on the decimated first group of signal statistics; generate a second predistortion term based on the second group of signal statistics; and generate an output predistortion terminal based on the first predistortion term and the second predistortion term.
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公开(公告)号：US20240297621A1
公开(公告)日：2024-09-05
申请号：US18592045
申请日：2024-02-29
Applicant: Texas Instruments Incorporated
Inventor： Jawaharlal Tangudu , Goutham Ramesh , Sarma Sundareswara Gunturi , Harsh Garg , Jaiganesh Balakrishnan , Mathews John , Sashidharan Venkatraman , Sanjay Pennam
CPC classification number: H03F1/3241 , H03F3/21 , H03F2201/3233
Abstract: An example method includes switching a first multiplexer circuit associated with first delay circuitry from (a) a first sub-lookup table (LUT) of a first LUT of digital pre-distortion (DPD) corrector circuitry to (b) a first corresponding sub-LUT of a second LUT of the DPD corrector circuitry, the first sub-LUT associated with the first delay circuitry, the second LUT storing updated values to compensate for non-linearity of power amplifier circuitry of a transmitter including the DPD corrector circuitry. The method includes, based on a value of a counter being equal to a difference between (1) a first delay of the first delay circuitry and (2) a second delay of second delay circuitry, switching a second multiplexer circuit associated with the second delay circuitry from (a) a second sub-LUT of the first LUT to (b) a second corresponding sub-LUT of the second LUT, the second sub-LUT associated with the second delay circuitry.
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公开(公告)号：US11356125B2
公开(公告)日：2022-06-07
申请号：US16953947
申请日：2020-11-20
Applicant: Texas Instruments Incorporated
Inventor： Jawaharlal Tangudu , Yeswanth Guntupalli , Kalyan Gudipati , Robert Clair Keller , Wenjing Lu , Jaiganesh Balakrishnan , Harsh Garg , Bragadeesh S , Raju Kharataram Chaudhari , Francesco Dantoni
Abstract: An integrated circuit comprises an input, a digital step attenuator, an analog-to-digital converter, a first output, a second output, a first bandwidth filter, a first band attack detector, a first band decay detector, a second bandwidth filter, a second band attack detector, a second band decay detector, and an automatic gain control. The ADC is configured to output a digital signal including a first and a second frequency range. The first and second bandwidth filters are configured to extract respective digital signals comprising the first and second frequency ranges. The band attack and decay detectors are configured to detect band peaks or decays thereof such that the DSA and External AMP may be controlled by means of the AGC based on the detected band peaks or decays, and ADC attack and ADC decay.
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公开(公告)号：US20210159924A1
公开(公告)日：2021-05-27
申请号：US16953947
申请日：2020-11-20
Applicant: Texas Instruments Incorporated
Inventor： Jawaharlal Tangudu , Yeswanth Guntupalli , Kalyan Gudipati , Robert Clair Keller , Wenjing Lu , Jaiganesh Balakrishnan , Harsh Garg , Bragadeesh S , Raju Kharataram Chaudhari , Francesco Dantoni
Abstract: An integrated circuit comprises an input, a digital step attenuator, an analog-to-digital converter, a first output, a second output, a first bandwidth filter, a first band attack detector, a first band decay detector, a second bandwidth filter, a second band attack detector, a second band decay detector, and an automatic gain control. The ADC is configured to output a digital signal including a first and a second frequency range. The first and second bandwidth filters are configured to extract respective digital signals comprising the first and second frequency ranges. The band attack and decay detectors are configured to detect band peaks or decays thereof such that the DSA and External AMP may be controlled by means of the AGC based on the detected band peaks or decays, and ADC attack and ADC decay.
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