Photon counting analog front end with load balancing

    公开(公告)号:US11543291B2

    公开(公告)日:2023-01-03

    申请号:US17245436

    申请日:2021-04-30

    Abstract: An analog front-end circuit includes an array of pixel circuits. Each pixel circuit includes an event counter and a power consumption circuit. The event counter is configured to count photons incident at the pixel circuit. The power compensation circuit includes an event rate circuit and a current sink circuit. The event rate circuit is configured to determine a rate of photon detection events at the pixel circuit. The current sink circuit is configured to pass a compensation current selected based on the rate of photon detection events at the pixel circuit.

    METHODS AND APPARATUS TO FORM AN IMAGE WITH DYNAMIC DELAY AND GAIN BEAMFORMING

    公开(公告)号:US20250007580A1

    公开(公告)日:2025-01-02

    申请号:US18755227

    申请日:2024-06-26

    Abstract: An example apparatus includes: at least one memory; programmable circuitry; and machine readable instructions to cause the programmable circuitry to at least: determine beamforming delay profiles for a plurality of channels, the beamforming delay profiles including delay values corresponding to a distance from a channel for a beamline; split the beamforming delay profiles into a plurality of segments; fit the plurality of segments of the beamforming delay profiles to linear segments; generate piece-wise beamforming delay profiles including initial values of the beamforming delay profiles, slopes of the linear segments of the plurality of segments, and durations of the plurality of segments; and store the piece-wise beamforming delay profiles for beamforming.

    METHODS AND APPARATUS TO FORM AN IMAGE WITH DYNAMIC DELAY AND GAIN BEAMFORMING

    公开(公告)号:US20250004116A1

    公开(公告)日:2025-01-02

    申请号:US18755238

    申请日:2024-06-26

    Abstract: An example apparatus includes: analog-to-digital converter (ADC) circuitry having an output terminal; beamforming circuitry including: delay circuitry having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the delay circuitry coupled to the output terminal of the ADC circuitry; amplifier circuitry having an input terminal and an output terminal, the input terminal of the amplifier circuitry coupled to the output terminal of the delay circuitry; and summation circuitry having an input terminal coupled to the output terminal of the amplifier circuitry; beamforming control circuitry coupled to the second input terminal of the delay circuitry, the beamforming control circuitry configured to calculate a delay value based on a piecewise delay profile.

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