公开(公告)号：US09407424B1

公开(公告)日：2016-08-02

申请号：US14682249

申请日：2015-04-09

Applicant: Texas Instruments Incorporated

Inventor： Bharathi Rahuldev Holla ,  Jagdish Chand Goyal ,  Biman Chattopadhyay ,  Sujoy Chakravarty ,  Sumantra Seth

IPC: H04L7/00

CPC classification number: H04L7/0337 ,  H04L7/0004

Abstract: A clock and data recovery module (CDR) is configured to perform fast locking using only two samples per each unit interval (UI). Two clock phase signals are selected from a plurality of clock phase signals. A sequence of data bits is sampled at a rate of two times per UI responsive to the two clock phase signals in which a first sample of each UI is designated as an edge sample a second sample is designated as a data sample. Each edge sample is voted as early/late as compared to an associated data transition of the sequence of data bits by comparing each edge sample to a next data sample. The sample clocks are locked such that edge samples occur in proximity to data transitions by iteratively adjusting a phase of the two selected clock phase signals by a variable step size in response to the early/late vote.

Abstract translation: 时钟和数据恢复模块（CDR）被配置为使用每个单位间隔（UI）仅使用两个采样来执行快速锁定。 从多个时钟相位信号中选择两个时钟相位信号。 响应于两个时钟相位信号，以每个UI两倍的速率对数据比特序列进行采样，其中将每个UI的第一样本指定为边缘样本，将第二样本指定为数据样本。 通过将每个边缘样本与下一个数据样本进行比较，与数据比特序列的相关数据转换相比，每个边缘样本被提前/晚选。 采样时钟被锁定，使得边缘采样在数据转换附近发生，通过响应于早/晚表决反复调整两个所选择的时钟相位信号的相位可变步长。