METHOD AND APPARATUS FOR SIMULATION MODELLING

    公开(公告)号:US20250117559A1

    公开(公告)日:2025-04-10

    申请号:US18481866

    申请日:2023-10-05

    Abstract: A method comprises creating an electronic circuit design having a plurality of electronic components, simulating operation of the electronic circuit design, and creating a behavior model of the electronic circuit design. The method further comprises eliminating one or more data points created in the behavior model to generate a trimmed behavior model, generating a real number model based on the trimmed behavior model, the real number model comprising a plurality of weights, and generating a simulation model based on the plurality of weights.

    INTEGRATED CIRCUIT DESIGN VERIFICATION
    3.
    发明公开

    公开(公告)号:US20240330549A1

    公开(公告)日:2024-10-03

    申请号:US18191863

    申请日:2023-03-28

    CPC classification number: G06F30/3308 G06F2119/02

    Abstract: In described examples, a method of testing an integrated circuit design under verification (DUV) includes selecting first and second stimulus-response data to generate a model, and adjusting model training data in response to model accuracy. The first stimulus-response data is selected from stimulus-response data for a known-good design similar to the DUV. The second stimulus-response data is selected from stimulus-response data for the DUV. The model is trained using the first and second stimulus-response data. A first correlation measure verifies model accuracy with respect to trained DUV stimulus-response data. A second correlation measure verifies model accuracy with respect to untrained DUV stimulus-response data. A fraction of trained DUV stimulus-response datasets in the second stimulus-response data is increased if the first correlation measure is greater than a first threshold, and a fraction of untrained DUV stimulus-response datasets is added if the second correlation measure is less than a second threshold.

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