公开(公告)号：US20250117559A1

公开(公告)日：2025-04-10

申请号：US18481866

申请日：2023-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ankush Ankush ,  Venkateswaran Padmanabhan ,  Aayush Garg ,  Guha Lakshmanan ,  Avishek Pal

IPC: G06F30/3308

Abstract: A method comprises creating an electronic circuit design having a plurality of electronic components, simulating operation of the electronic circuit design, and creating a behavior model of the electronic circuit design. The method further comprises eliminating one or more data points created in the behavior model to generate a trimmed behavior model, generating a real number model based on the trimmed behavior model, the real number model comprising a plurality of weights, and generating a simulation model based on the plurality of weights.

公开(公告)号：US20240330549A1

公开(公告)日：2024-10-03

申请号：US18191863

申请日：2023-03-28

Applicant: Texas Instruments Incorporated

Inventor： Danyal Shamsi ,  Venkata Naresh Kotikelapudi ,  Venkateswaran Padmanabhan ,  Guha Lakshmanan ,  Saksham Sangwan

IPC: G06F30/3308

CPC classification number: G06F30/3308 ,  G06F2119/02

Abstract: In described examples, a method of testing an integrated circuit design under verification (DUV) includes selecting first and second stimulus-response data to generate a model, and adjusting model training data in response to model accuracy. The first stimulus-response data is selected from stimulus-response data for a known-good design similar to the DUV. The second stimulus-response data is selected from stimulus-response data for the DUV. The model is trained using the first and second stimulus-response data. A first correlation measure verifies model accuracy with respect to trained DUV stimulus-response data. A second correlation measure verifies model accuracy with respect to untrained DUV stimulus-response data. A fraction of trained DUV stimulus-response datasets in the second stimulus-response data is increased if the first correlation measure is greater than a first threshold, and a fraction of untrained DUV stimulus-response datasets is added if the second correlation measure is less than a second threshold.

公开(公告)号：US20250117560A1

公开(公告)日：2025-04-10

申请号：US18481711

申请日：2023-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saksham Sangwan ,  Venkateswaran Padmanabhan ,  Guha Lakshmanan

IPC: G06F30/367 ,  G06F111/10 ,  G06N3/063

Abstract: A method comprises creating an electronic circuit design having a plurality of electronic components, creating an analog simulation model of the electronic circuit design, and executing the analog simulation model to generate one or more simulation logs representing simulated operation of the electronic circuit design. The method also comprises generating a neural network model based on the one or more simulation logs, the neural network model comprising a plurality of weights and generating a mathematical simulation model based on the neural network model.

公开(公告)号：US20210208197A1

公开(公告)日：2021-07-08

申请号：US17139246

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Guha Lakshmanan ,  Rakesh Hariharan ,  Lakshmanan Balasubramanian

IPC: G01R31/317 ,  G01R3/00

Abstract: A packaged electronic device has a die with a load circuit, a resistor and an analog to digital converter (ADC). The resistor is coupled between a supply node of the die and a power input of the load circuit. The ADC has a first input coupled to a first terminal of the resistor, and a second input coupled to a second terminal of the resistor to measure a voltage across the resistor while a supply voltage is applied to the supply node to determine a load current conducted by the load circuit. A method of manufacturing a packaged electronic device includes wafer processing to fabricate the load circuit, the resistor and the ADC on or in a die area of the wafer with the resistor coupled between the power input of the load circuit and the supply node of the die area.