公开(公告)号：US20100142931A1

公开(公告)日：2010-06-10

申请号：US12330338

申请日：2008-12-08

申请人： Thanh T. Tran ,  Todd C. Hiers ,  Ivan Garcia ,  Jian Wang

发明人： Thanh T. Tran ,  Todd C. Hiers ,  Ivan Garcia ,  Jian Wang

IPC分类号： H04N7/01 ,  G09G5/36

CPC分类号： G09G5/363 ,  G09G2320/0252 ,  G09G2360/06 ,  G09G2360/121 ,  G09G2360/18 ,  H04N19/436 ,  H04N19/61

摘要： A system and method for allocating video processing tasks over multiple video processors include an apparatus. The apparatus includes a plurality of video processors. Each video processor includes a first processor that processes video data and manages buffers used in conversion and displaying video data. The video processor includes a second processor that performs video data signal processing and manages buffers used in processing video data. The apparatus also includes a switch coupled to each video processor, as well as video inputs and video outputs. A third processor coupled to the switch, and a memory coupled to each video processor and to the third processor, are also part of the apparatus. The switch selectively couples a video processor to a video input or a video output, the third processor configures the switch based on processing requirements of each video stream, and the memory buffers and stores video data.

摘要翻译： 用于在多个视频处理器上分配视频处理任务的系统和方法包括一种装置。 该装置包括多个视频处理器。 每个视频处理器包括处理视频数据并管理用于转换和显示视频数据的缓冲器的第一处理器。 视频处理器包括执行视频数据信号处理并管理在处理视频数据中使用的缓冲器的第二处理器。 该装置还包括耦合到每个视频处理器的开关，以及视频输入和视频输出。 耦合到开关的第三处理器和耦合到每个视频处理器和第三处理器的存储器也是该装置的一部分。 开关将视频处理器选择性地耦合到视频输入或视频输出，第三处理器基于每个视频流的处理要求配置开关，并且存储器缓冲并存储视频数据。

公开(公告)号：US08380053B2

公开(公告)日：2013-02-19

申请号：US12330338

申请日：2008-12-08

申请人： Thanh T. Tran ,  Todd C. Hiers ,  Ivan Garcia ,  Jian Wang

发明人： Thanh T. Tran ,  Todd C. Hiers ,  Ivan Garcia ,  Jian Wang

IPC分类号： H04N5/917

CPC分类号： G09G5/363 ,  G09G2320/0252 ,  G09G2360/06 ,  G09G2360/121 ,  G09G2360/18 ,  H04N19/436 ,  H04N19/61

摘要： A system and method for allocating video processing tasks over multiple video processors include an apparatus. The apparatus includes a plurality of video processors. Each video processor includes a first processor that processes video data and manages buffers used in conversion and displaying video data. The video processor includes a second processor that performs video data signal processing and manages buffers used in processing video data. The apparatus also includes a switch coupled to each video processor, as well as video inputs and video outputs. A third processor coupled to the switch, and a memory coupled to each video processor and to the third processor, are also part of the apparatus. The switch selectively couples a video processor to a video input or a video output, the third processor configures the switch based on processing requirements of each video stream, and the memory buffers and stores video data.

摘要翻译： 用于在多个视频处理器上分配视频处理任务的系统和方法包括一种装置。 该装置包括多个视频处理器。 每个视频处理器包括处理视频数据并管理用于转换和显示视频数据的缓冲器的第一处理器。 视频处理器包括执行视频数据信号处理并管理在处理视频数据中使用的缓冲器的第二处理器。 该装置还包括耦合到每个视频处理器的开关，以及视频输入和视频输出。 耦合到开关的第三处理器和耦合到每个视频处理器和第三处理器的存储器也是该装置的一部分。 开关将视频处理器选择性地耦合到视频输入或视频输出，第三处理器基于每个视频流的处理要求配置开关，并且存储器缓冲并存储视频数据。

公开(公告)号：US20090158379A1

公开(公告)日：2009-06-18

申请号：US12334807

申请日：2008-12-15

申请人： Todd C. Hiers

发明人： Todd C. Hiers

IPC分类号： H04N7/173

CPC分类号： H04N21/4347 ,  H04N21/23406 ,  H04N21/2365

摘要： A video port aggregator receives plural asynchronous video data streams. Corresponding input buffers generate video data and a status signal. A memory controller writes the video data in corresponding locations within an external memory. A channel triggers the memory controller to read data out of the external memory for transmission to a single video output port when said corresponding status signal indicates receipt of a predetermined portion of data. This read out of the external memory being faster than the writing. The channel sequencer triggers the memory controller to read data out of the external memory video data of a highest priority asynchronous video data stream having a received next portion of data.

摘要翻译： 视频端口聚合器接收多个异步视频数据流。 相应的输入缓冲器产生视频数据和状态信号。 存储器控制器将视频数据写入外部存储器内的相应位置。 当所述对应的状态信号指示接收到预定数据部分时，通道触发存储器控制器从外部存储器读取数据以传输到单个视频输出端口。 读出的外部存储器比写入速度要快。 信道定序器触发存储器控制器从具有接收的下一部分数据的最高优先级异步视频数据流的外部存储器视频数据中读出数据。

公开(公告)号：US08443413B2

公开(公告)日：2013-05-14

申请号：US12334807

申请日：2008-12-15

申请人： Todd C. Hiers

发明人： Todd C. Hiers

IPC分类号： H04N7/173

CPC分类号： H04N21/4347 ,  H04N21/23406 ,  H04N21/2365

摘要： A video port aggregator receives plural asynchronous video data streams. Corresponding input buffers generate video data and a status signal. A memory controller writes the video data in corresponding locations within an external memory. A channel triggers the memory controller to read data out of the external memory for transmission to a single video output port when said corresponding status signal indicates receipt of a predetermined portion of data. This read out of the external memory being faster than the writing. The channel sequencer triggers the memory controller to read data out of the external memory video data of a highest priority asynchronous video data stream having a received next portion of data.

摘要翻译： 视频端口聚合器接收多个异步视频数据流。 相应的输入缓冲器产生视频数据和状态信号。 存储器控制器将视频数据写入外部存储器内的相应位置。 当所述对应的状态信号指示接收到预定数据部分时，通道触发存储器控制器从外部存储器读取数据以传输到单个视频输出端口。 读出的外部存储器比写入速度要快。 信道定序器触发存储器控制器从具有接收的下一部分数据的最高优先级异步视频数据流的外部存储器视频数据中读出数据。