公开(公告)号：US20200328877A1

公开(公告)日：2020-10-15

申请号：US16845556

申请日：2020-04-10

Applicant: The Board of Regents of the University of Texas System

Inventor： Alekhya MUTHINENI ,  Eugene JOHN

IPC: H04L9/06 ,  G06F1/26

Abstract: The present techniques may provide improved processing and functionality of performance of the 128-bit AES Algorithm, which may provide improved power consumption. For example, in an embodiment, an encryption and decryption apparatus may comprise memory storing a current state matrix of an encryption or decryption process and a plurality of multiplexers configured to receive from the memory current elements of the state matrix stored in the memory, perform a cyclic shift on the received elements of the state matrix, and transmit the shifted elements to the memory for storage as a new state matrix.

公开(公告)号：US20240187212A1

公开(公告)日：2024-06-06

申请号：US18525260

申请日：2023-11-30

Applicant: The Board of Regents of the University of Texas System

Inventor： Alekhya MUTHINENI ,  Eugene JOHN

IPC: H04L9/06 ,  G06F1/26

CPC classification number: H04L9/0631 ,  G06F1/26

Abstract: The present techniques may provide improved processing and functionality of performance of the 128-bit AES Algorithm, which may provide improved power consumption. For example, in an embodiment, an encryption and decryption apparatus may comprise memory storing a current state matrix of an encryption or decryption process and a plurality of multiplexers configured to receive from the memory current elements of the state matrix stored in the memory, perform a cyclic shift on the received elements of the state matrix, and transmit the shifted elements to the memory for storage as a new state matrix.