公开(公告)号：US20210399121A1

公开(公告)日：2021-12-23

申请号：US17353665

申请日：2021-06-21

Applicant: The Regents of the University of California

Inventor： Brian Romanczyk ,  Umesh K. Mishra ,  Pawana Shrestha ,  Matthew Guidry ,  James Buckwalter ,  Stacia Keller ,  Rohit Reddy Karnaty

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/267

Abstract: Derivative cancellation techniques have been used to linearize transistors using multiple discreet devices. However at frequencies approaching and in the mm-wave regime the use of individual devices no longer works due to the parasitics associated with combining the devices. In this invention device structures are described which apply the derivative cancellation technique in a single device thus removing the detrimental impact of combining. In one example, an N-polar transistor structure includes a channel; a cap structure comprising a plurality of cap layers on or above the channel; a source contact and a drain contact to the channel; and a castellated, stepped, or varying pattern formed in the cap layers so that gate metal deposited on the pattern forms at least two different threshold voltages and current combines in the ohmic region with essentially zero parasitic inductance.