公开(公告)号：US20250037028A1

公开(公告)日：2025-01-30

申请号：US18782768

申请日：2024-07-24

Applicant: The Trustees of Princeton University

Inventor： Shikhar Tuli ,  Niraj K. Jha

IPC: G06N20/00 ,  G06N5/04

Abstract: Methods for co-designing transformer-accelerator pairs are provided. The methods may include using a transformer embedding to generate a computational graph and a transformer model. The methods may include running the computational graph through a surrogate model and outputting accuracy data of the surrogate model. The methods may include using an accelerator embedding and the transformer model to simulate training and inference tasks and outputting hardware performance data of the transformer model. The methods may include sending the hardware performance data (such as latency, energy leakage, dynamic energy, and chip area, which may be optimizable performance parameters) and model accuracy data to a co-design optimizer. The methods may include generating an output transformer-accelerator or a transformer-edge-device pair from the co-design optimizer. The transformer model and accelerator embedding may be the output transformer-accelerator or a transformer-edge-device pair.