公开(公告)号：US11544066B2

公开(公告)日：2023-01-03

申请号：US16971419

申请日：2019-02-11

申请人： The University Court of the University of Edinburgh

发明人： Rakesh Kumar ,  Boris Grot ,  Vijay Nagarajan

IPC分类号： G06F9/38

摘要： A branch target buffer, BTB, is provided to store at least one BTB entry corresponding to a respective branch in a control flow in a sequence of machine-readable instructions of a computer program. The BTB has a tag field to compare with a program counter of a fetch address generator and at least one further field to store information characteristic of the branch instruction identified by the corresponding tag field and allowing a conditional branch to be distinguished from an unconditional branch instruction. The BTB has a predetermined storage capacity and is utilized such that unconditional branch instructions are preferentially allocated storage space in the BTB relative to conditional branch instructions.

公开(公告)号：US20210004233A1

公开(公告)日：2021-01-07

申请号：US16971419

申请日：2019-02-11

申请人： The University Court of the University of Edinburgh

发明人： Rakesh Kumar ,  Boris Grot ,  Vijay Nagarajan

IPC分类号： G06F9/38

摘要： A branch target buffer, BTB, is provided to store at least one BTB entry corresponding to a respective branch in a control flow in a sequence of machine-readable instructions of a computer program. The BTB has a tag field to compare with a program counter of a fetch address generator and at least one further field to store information characteristic of the branch instruction identified by the corresponding tag field and allowing a conditional branch to be distinguished from an unconditional branch instruction. The BTB has a predetermined storage capacity and is utilized such that unconditional branch instructions are preferentially allocated storage space in the BTB relative to conditional branch instructions.

公开(公告)号：US11269641B2

公开(公告)日：2022-03-08

申请号：US16483198

申请日：2018-02-01

申请人： THE UNIVERSITY COURT OF THE UNIVERSITY OF EDINBURGH

发明人： Rakesh Kumar ,  Boris Grot ,  Vijay Nagarajan ,  Cheng Chieh Huang

IPC分类号： G06F9/38 ,  G06F9/30

摘要： A data processing apparatus is provided having branch prediction circuitry, the branch prediction circuitry having a Branch Target Buffer, BTB. A fetch target queue receives entries corresponding to a sequence of instruction addresses, at least one of the sequence having been predicted using the branch prediction circuitry. A fetch engine is provided to fetch instruction addresses taken from a top of the fetch target queue whilst a prefetch engine sends a prefetch probe to an instruction cache. The BTB is to detect a BTB miss when attempting to populate a storage slot of the fetch target queue and the BTB triggers issuance of a BTB miss probe to the memory to fetch at least one instruction from the memory to resolve the BTB miss using branch-prediction based prefetching.