公开(公告)号：US06429712B1

公开(公告)日：2002-08-06

申请号：US09941875

申请日：2001-08-29

申请人： Thomas A. Gaiser ,  Kenneth J. Stern ,  Farhad Vazehgoo ,  Vincenzo DiTommaso ,  William L. Walter ,  Edward B. Hilton

发明人： Thomas A. Gaiser ,  Kenneth J. Stern ,  Farhad Vazehgoo ,  Vincenzo DiTommaso ,  William L. Walter ,  Edward B. Hilton

IPC分类号： H03K3037

CPC分类号： H03K3/012 ,  H03K3/037 ,  H03K17/603 ,  H03K17/6264

摘要： A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through. the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

摘要翻译： 精确的SET-RESET逻辑电路和操作方法将锁存功能与产生逻辑输出的关键信号路径分开。 在特定实现中，逻辑电路包括分别由SET和RESET输入控制的两个差分开关对，以及由锁存电路的输出控制的差分对的各个使能电路。 SET和RESET差分开关对响应快于锁存电路以改变输入SET-RESET状态。 最初通过建立第一个当前路径来产生逻辑输出。 差分开关和使能电路响应于新的逻辑输入，然后通过不同的电流路径锁存。

公开(公告)号：US06326828B1

公开(公告)日：2001-12-04

申请号：US09456748

申请日：1999-12-07

申请人： Thomas A. Gaiser ,  Kenneth J. Stern ,  Farhad Vazehgoo ,  Vincenzo DiTommaso ,  William L. Walter ,  Edward B. Hilton

发明人： Thomas A. Gaiser ,  Kenneth J. Stern ,  Farhad Vazehgoo ,  Vincenzo DiTommaso ,  William L. Walter ,  Edward B. Hilton

IPC分类号： H03K3037

CPC分类号： H03K3/012 ,  H03K3/037 ,  H03K17/603 ,  H03K17/6264

摘要： A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

摘要翻译： 精确的SET-RESET逻辑电路和操作方法将锁存功能与产生逻辑输出的关键信号路径分开。 在特定实现中，逻辑电路包括分别由SET和RESET输入控制的两个差分开关对，以及由锁存电路的输出控制的差分对的各个使能电路。 SET和RESET差分开关对响应快于锁存电路以改变输入SET-RESET状态。 最初通过建立通过差分开关和使能电路的第一电流路径响应于新的逻辑输入而产生逻辑输出，然后通过不同的电流路径锁存。

公开(公告)号：US5434446A

公开(公告)日：1995-07-18

申请号：US287478

申请日：1994-08-08

申请人： Edward B. Hilton ,  Robert A. Duris ,  Douglas W. Babcock

发明人： Edward B. Hilton ,  Robert A. Duris ,  Douglas W. Babcock

IPC分类号： H01L27/12 ,  H01L27/02

CPC分类号： H01L27/1203

摘要： A parasitic capacitance cancellation circuit for a direct bonded silicon-on-insulator integrated circuit includes one or more transistors fabricated silicon-on-insulator; a silicon substrate region outside the transistor(s) having a parasitic capacitance to be cancelled; a bootstrap terminal connected to the region outside the transistor(s); and a unity gain buffer responsive to the output of the transistor(s) and having its output connected to the bootstrap terminals for providing a voltage to the region outside the transistor(s) which follows the voltage developed on the parasitic capacitance and nullifies the parasitic capacitance.

摘要翻译： 用于直接键合绝缘体上硅的集成电路的寄生电容消除电路包括一个或多个制造在绝缘体上的晶体管; 晶体管外部的硅衬底区域具有要消除的寄生电容; 连接到所述晶体管外部的区域的自举端子; 以及响应于晶体管的输出并且其输出连接到自举端子的单位增益缓冲器，用于向跟随在寄生电容上产生的电压的晶体管之外的区域提供电压，并且使寄生 电容。