Memory stacking system and method
    1.
    发明授权
    Memory stacking system and method 有权
    内存堆叠系统和方法

    公开(公告)号:US07269042B2

    公开(公告)日:2007-09-11

    申请号:US11413793

    申请日:2006-04-28

    IPC分类号: G11C5/00 G11C7/00

    CPC分类号: G11C5/04 G11C5/02 G11C8/12

    摘要: A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a logic block for decoding a plurality of chip select signals. A first high density memory module is also provided that includes the modified memory devices and a serial presence detect device. The first high density memory module is included within an electronic system. Also, an additional method of forming a stacked memory module is provided, the method requiring modification of an address buffer to include a logic block for decoding a plurality of chip select signals. A second high density memory module is also provided that includes the modified address buffer and a serial presence detect device. The second high density memory module is included within an electronic system.

    摘要翻译: 提供了一种从多个存储器件形成堆叠的存储器模块的方法。 多个存储器件中的每一个被修改为包括用于解码多个片选信号的逻辑块。 还提供了包括经修改的存储器件和串行存在检测器件的第一高密度存储器模块。 第一高密度存储器模块包括在电子系统内。 此外,提供了形成堆叠存储器模块的附加方法,该方法需要修改地址缓冲器以包括用于解码多个片选信号的逻辑块。 还提供了第二高密度存储器模块,其包括修改的地址缓冲器和串行存在检测器件。 第二高密度存储器模块包括在电子系统内。

    Memory stacking system and method

    公开(公告)号:US07046538B2

    公开(公告)日:2006-05-16

    申请号:US10932834

    申请日:2004-09-01

    IPC分类号: G11C5/02 G11C8/00

    CPC分类号: G11C5/04 G11C5/02 G11C8/12

    摘要: A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a logic block for decoding a plurality of chip select signals. A first high density memory module is also provided that includes the modified memory devices and a serial presence detect device. The first high density memory module is included within an electronic system. Also, an additional method of forming a stacked memory module is provided, the method requiring modification of an address buffer to include a logic block for decoding a plurality of chip select signals. A second high density memory module is also provided that includes the modified address buffer and a serial presence detect device. The second high density memory module is included within an electronic system.