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公开(公告)号：US06233639B1
公开(公告)日：2001-05-15
申请号：US09225524
申请日：1999-01-04
IPC分类号： G06F1300
CPC分类号： G11C5/066
摘要： A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory card to gain access to the system device without using the system memory bus. The serial bus is a two wire serial bus connecting the device to the DSP through the system memory controller. If more than one memory card is present with DSPs or more than one device is contending for access, the system memory controller or arbitrate the access of each memory card or contending device. In such case the serial bus will signal the system memory controller when it wants access to the particular device, and the system memory controller will act as arbitrator to grant or not grant access to the particular memory card or device requesting access. If access is granted the bus memory controller outputs the required control or command word on the serial bus followed by the address and the required data. This serial information is received by the system memory controller which packets it, and, upon completion, outputs the information rapidly on a parallel bus, e.g. a PCI bus to the device which needs the information.
摘要翻译： 在具有DSP和存储器总线控制器的存储卡上提供串行总线和通过系统存储器控制器与计算机系统上的设备的连接，以允许存储卡上的DSP访问系统设备而不使用系统 内存总线 串行总线是通过系统存储器控制器将设备连接到DSP的双线串行总线。 如果多个存储卡存在于DSP或多于一个设备正在争取访问，则系统存储器控制器或仲裁每个存储卡或竞争设备的访问。 在这种情况下，当串行总线想要访问特定设备时，串行总线将向系统存储器控制器发信号通知，并且系统存储器控制器将充当仲裁器以授予或不授予对请求访问的特定存储卡或设备的访问权限。 如果访问被授予，总线存储器控制器在串行总线上输出所需的控制或命令字，然后输出地址和所需的数据。 该串行信息由系统存储器控制器接收，该系统存储器控制器对其进行分组，并且在完成时，在并行总线上快速地输出信息，例如， PCI总线到需要信息的设备。
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公开(公告)号：US06385685B1
公开(公告)日：2002-05-07
申请号：US09833871
申请日：2001-04-12
IPC分类号： G06F1338
CPC分类号： G11C5/066
摘要： A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory card to gain access to the system device without using the system memory bus. The serial bus is a two wire serial bus connecting the device to the DSP through the system memory controller. If more than one memory card is present with DSPs or more than one device is contending for access, the system memory controller or arbitrate the access of each memory card or contending device. In such case the serial bus will signal the system memory controller when it wants access to the particular device, and the system memory controller will act as arbitrator to grant or not grant access to the particular memory card or device requesting access. If access is granted the bus memory controller outputs the required control or command word on the serial bus followed by the address and the required data. This serial information is received by the system memory controller which packets it, and, upon completion, outputs the information rapidly on a parallel bus, e.g. a PCI bus to the device which needs the information.
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公开(公告)号：US06446163B1
公开(公告)日：2002-09-03
申请号：US09386543
申请日：1999-08-31
IPC分类号： G06F1206
CPC分类号： G11C5/066
摘要： A memory card having a memory bus controller is provided which card has a signal processing element preferably a digital signal processor (DSP) thereon, which card is used in a computer system as add-on memory. Also, a method of using such a card in a computer system is provided. The memory bus controller and the signal processing element are programmed to pass all the addresses in the memory on the card and the associated data received from the CPU to the signal processing element where they are stored in memory. The signal processing element is programmed to perform selected operations on the addresses and/data irrespective of whether the signal processing element has control of the system bus. These operations can include keeping track of read/write operations and the locations of these operations. This information can be easily accessed by the computer system and used for memory optimization. The DSP can also “snoop” the memory bus when it is unavailable to the control of the DSP, i.e. when the system has control of the memory bus. The memory bus controller passes addresses and data to the DSP as it is received. When the DSP receives addresses that are in its normal or regular range, or other selected ranges, for processing in the memory. The DSP can capture the data and do “early” processing or pre-processing of this information before the DSP gains control of the memory.
摘要翻译： 提供了具有存储器总线控制器的存储卡，该卡具有信号处理元件，优选地在其上的数字信号处理器（DSP），该卡在计算机系统中用作附加存储器。 另外，提供了一种在计算机系统中使用这种卡的方法。 存储器总线控制器和信号处理元件被编程为将卡上的存储器中的所有地址以及从CPU接收的相关数据传送到存储在存储器中的信号处理元件。 信号处理元件被编程为对地址和/数据执行选择的操作，而不管信号处理元件是否具有对系统总线的控制。 这些操作可以包括跟踪读/写操作和这些操作的位置。 该信息可以被计算机系统容易地访问并且用于存储器优化。当DSP对DSP的控制不可用时，即当系统具有对存储器总线的控制时，DSP也可以“窥探”存储器总线。 存储器总线控制器将地址和数据传送到DSP，因为它被接收。 当DSP接收到正常或正常范围或其他选定范围的地址时，用于在存储器中进行处理。 DSP可以捕获数据，并在DSP获得对存储器的控制之前对该信息进行“早期”处理或预处理。
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公开(公告)号：US5550768A
公开(公告)日：1996-08-27
申请号：US381783
申请日：1995-01-31
CPC分类号： G06F5/012
摘要： A method and apparatus for parallel "normalize-round-normalize" floating point arithmetic. The rounding-normalizer of the invention receives as an input an infinitely precise mantissa which is the result of a floating point operation. This infinitely precise result mantissa is broken into two fields, the Close Enough Bits, and the Picky Bits. These bits are selectively passed to four parallel data paths for taking close enough bits and picky bits and producing a correctly rounded mantissa. The paths are, respectively; (a) a 1X.XX . . . X data path for mantissas greater than or equal to 2 but less than 4, the data path right shifting the upper bits and adjusting the exponent by +1 or +2; (b) a 01.XX . . . X data path for mantissas greater than or equal to 1 but less than 2, the data path right shifting the upper bits and adjusting the exponents by +0 or +1; (c) a 00.1X . . . X data path for mantissas greater than or equal to 1/2 but less than 1, the data path left shifting bits and adjusting the exponent by -1 or +0; and (d) a 00.01X . . . X data path for mantissas less than 1/2, the data path left shifting the bits and adjusting the exponent by the shift amount. Each of the data paths produces a normalized and rounded mantissa for its subset of mantissas.
摘要翻译： 用于并行“归一化 - 归一化”浮点运算的方法和装置。 本发明的舍入式归一化器作为输入接收作为浮点运算结果的无限精确尾数。 这个无限精确的结果尾数被分为两个字段，即关闭足够的位和拾取位。 这些位被选择性地传递到四个并行数据路径以获取足够近的位和挑选位并产生正确舍入的尾数。 路径分别为： （a）1X.XX。 。 。 X数据路径为大于或等于2但小于4，数据路径右移高位，并将指数调整+1或+2; （b）01.XX。 。 。 X数据路径大于或等于1，但数据路径右移高位，并将指数调整为+0或+1; （c）00.1X。 。 。 X数据路径大于或等于+ E，fra 1/2 + EE但小于1，数据路径左移位，并将指数调整-1或+0; 和（d）00.01X。 。 。 X数据路径小于+ E，fra 1/2 + EE，数据路径左移位并将指数调整移位量。 每个数据路径为其子集的尾数产生归一化和舍入的尾数。
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