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公开(公告)号：US06771131B2
公开(公告)日：2004-08-03
申请号：US10142492
申请日：2002-05-09
IPC分类号： H03F308
CPC分类号： H03F3/45183 , H03F3/082 , H03F2203/45644 , H03F2203/45728
摘要： A CMOS amplifier for optoelectronic receivers, the amplifier comprises two transimpedance amplifiers and two differential amplifier latches. One of the two transimpedance amplifiers has an input port to receive a current signal, such as, for example, a current signal from a photodetector, and provides a output voltage indicative of the received current signal. The other of the two transimpedance amplifiers may be viewed as having no input signal, so that it provides a reference voltage. The two transimpedance amplifiers are in close proximity to each other, so that power supply noise is a common mode signal in the output voltages of the two transimpedance amplifiers. The differential amplifier latches reject the common mode signal by comparing the reference voltage to the output voltage, and provide output logic voltages indicative of binary hard decisions. Two differential amplifier latches are employed, each with an evaluation phase on alternate transitions of a clock signal, so as to provide a higher throughput than if only one differential amplifier latch was employed.
摘要翻译： 用于光电子接收器的CMOS放大器，放大器包括两个跨阻放大器和两个差分放大器锁存器。 两个跨阻放大器中的一个具有用于接收电流信号的输入端口，例如来自光电检测器的电流信号，并且提供指示接收的电流信号的输出电压。 两个跨阻放大器中的另一个可以被视为没有输入信号，从而提供参考电压。 两个跨阻放大器彼此靠近，使得电源噪声是两个跨阻放大器的输出电压中的共模信号。 差分放大器锁存器通过将参考电压与输出电压进行比较来拒绝共模信号，并提供指示二进制硬判决的输出逻辑电压。 采用两个差分放大器锁存器，每个差分放大器锁存器具有时钟信号的交替转换的评估阶段，以便提供比仅采用一个差分放大器锁存器更高的吞吐量。
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公开(公告)号：US07301391B2
公开(公告)日：2007-11-27
申请号：US11181380
申请日：2005-07-14
CPC分类号： G06G7/16 , H03H11/1213
摘要： A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output signal. The tail currents can be advantageously varied with variable current sources or by adjustment of the relative widths of the differential transistor pairs. In other embodiments, additional differential pairs can be added to adjust for systematic offset voltages caused by process-induced variations in the structure of circuit devices or to induce a desired offset.
摘要翻译： 可以用多个差分输入级和可变尾电流来实现电流求和FIR滤波器。 可变尾电流可用于适当地加权当前和以前的数字输入信号。 可以将差分晶体管对的加权输出相加以提供经滤波的输出信号。 可以利用可变电流源或通过调整差分晶体管对的相对宽度来有利地改变尾电流。 在其他实施例中，可以添加额外的差分对以调整由电路装置的结构中的过程引起的变化引起的系统偏移电压或引起期望的偏移。
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4.发明授权公开(公告)号：US07177288B2
公开(公告)日：2007-02-13
申请号：US09998008
申请日：2001-11-28
申请人： Stephen R. Mooney , Aaron K. Martin , Matthew B. Haycock , Bryan K. Casper , Shekhar Y. Borkar , Joseph T. Kennedy , James E. Jaussi
发明人： Stephen R. Mooney , Aaron K. Martin , Matthew B. Haycock , Bryan K. Casper , Shekhar Y. Borkar , Joseph T. Kennedy , James E. Jaussi
IPC分类号： H04L5/14
CPC分类号： H04L5/1423
摘要： A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.
摘要翻译： 一种设备包括总线，连接到总线的第一发射机，并且被配置为在第一频带中通过总线传输第一信号，第二发射器连接到总线并且被配置为以第二频率通过总线发送第二信号 与第一发射机正在发送第一信号的同时，连接到总线并被配置为接收通过总线在第一频带中发送的第一信号的第一接收机和连接到总线的第二接收机，并且被配置为 接收在第二频带中通过总线发送的第二信号。 第一频带和第二频带占据频谱的不同部分。
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公开(公告)号：US06621323B1
公开(公告)日：2003-09-16
申请号：US10131443
申请日：2002-04-24
IPC分类号： H03K1730
CPC分类号： H04L25/0292 , G11C27/024 , H04L5/1423 , H04L25/0272 , H04L25/028
摘要： A circuit samples a voltage on a simultaneous bi-directional bus, and subtracts an outbound voltage to determine an inbound voltage. Sampling capacitors are variable to adjust for matching time constants. A mechanism is provided to sample error voltages over clock phase variations and sampling capacitor values.
摘要翻译： 电路对同时双向总线上的电压进行采样，并减去出站电压以确定入站电压。 采样电容是可变的，用于调整匹配的时间常数。 提供了一种机制来对时钟相位变化和采样电容值进行误差电压的采样。
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公开(公告)号：US20080181331A1
公开(公告)日：2008-07-31
申请号：US12077987
申请日：2008-03-24
申请人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
发明人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
CPC分类号： H04L25/4917
摘要： A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.
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公开(公告)号：US06624688B2
公开(公告)日：2003-09-23
申请号：US10041677
申请日：2002-01-07
IPC分类号： H03F345
CPC分类号： G06G7/16 , H03H11/1213
摘要： A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output signal. The tail currents can be advantageously varied with variable current sources or by adjustment of the relative widths of the differential transistor pairs. In other embodiments, additional differential pairs can be added to adjust for systematic offset voltages caused by process-induced variations in the structure of circuit devices or to induce a desired offset.
摘要翻译： 可以用多个差分输入级和可变尾电流来实现电流求和FIR滤波器。 可变尾电流可用于适当地加权当前和以前的数字输入信号。 可以将差分晶体管对的加权输出相加以提供经滤波的输出信号。 可以利用可变电流源或通过调整差分晶体管对的相对宽度来有利地改变尾电流。 在其他实施例中，可以添加额外的差分对以调整由电路装置的结构中的过程引起的变化引起的系统偏移电压或引起期望的偏移。
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公开(公告)号：US07457393B2
公开(公告)日：2008-11-25
申请号：US11025771
申请日：2004-12-29
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , H03L7/0814 , H03L7/18 , H04L7/0008 , H04L7/0025 , H04L7/10
摘要： A global clock recovery circuit and port circuit determine and combine static phase adjustment information and dynamic phase adjustment information for multiple data signals. Static phase adjustment information is determined for each of the multiple data signals, and dynamic phase adjustment information is determined in common for the multiple data signals.
摘要翻译： 全局时钟恢复电路和端口电路确定并组合多个数据信号的静态相位调整信息和动态相位调整信息。 为多个数据信号中的每一个确定静态相位调整信息，并且为多个数据信号共同确定动态相位调整信息。
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公开(公告)号：US06946902B2
公开(公告)日：2005-09-20
申请号：US10626491
申请日：2003-07-24
CPC分类号： G06G7/16 , H03H11/1213
摘要： A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output signal. The tail currents can be advantageously varied with variable current sources or by adjustment of the relative widths of the differential transistor pairs. In other embodiments, additional differential pairs can be added to adjust for systematic offset voltages caused by process-induced variations in the structure of circuit devices or to induce a desired offset.
摘要翻译： 可以用多个差分输入级和可变尾电流来实现电流求和FIR滤波器。 可变尾电流可用于适当地加权当前和以前的数字输入信号。 可以将差分晶体管对的加权输出相加以提供经滤波的输出信号。 可以利用可变电流源或通过调整差分晶体管对的相对宽度来有利地改变尾电流。 在其他实施例中，可以添加额外的差分对以调整由电路装置的结构中的过程引起的变化引起的系统偏移电压或引起期望的偏移。
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公开(公告)号：US06621330B1
公开(公告)日：2003-09-16
申请号：US10162936
申请日：2002-06-04
IPC分类号： H03B100
CPC分类号： H03H15/00
摘要： A discrete-time analog filter, where a filter tap of the filter comprises a voltage-to-current converter and a current multiplier in a single stage so as to provide a current signal indicative of a weighted sampled voltage signal. The current signals are summed by one or more active cascode differential latches to provide an output logic signal indicative of the filtered output. The discrete-time analog filter finds applications in channel equalization, and is suitable for high data rates and low voltage applications. The voltage and current signals may be differential.
摘要翻译： 离散时间模拟滤波器，其中滤波器的滤波器抽头包括电压 - 电流转换器和单级中的电流倍增器，以便提供指示加权采样电压信号的电流信号。 当前信号由一个或多个有源共源共栅差分锁存器相加以提供指示滤波输出的输出逻辑信号。 离散时间模拟滤波器可用于信道均衡，适用于高数据速率和低电压应用。 电压和电流信号可能是差分的。
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