公开(公告)号：US06766154B2

公开(公告)日：2004-07-20

申请号：US09800699

申请日：2001-03-07

申请人： Todd E. Humes ,  Kenneth K. Tsai ,  Talley J. Allen ,  Mark Kintis

发明人： Todd E. Humes ,  Kenneth K. Tsai ,  Talley J. Allen ,  Mark Kintis

IPC分类号： H04B700

CPC分类号： H03L7/18 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/107 ,  H03L7/1075 ,  H03L2207/04

摘要： Fast switching and fast settling is achieved in a phase locked loop (“PLL”) containing a bandwidth switched active loop filter (8) by feeding the phase error signal of the phase detector (1) of the PLL to the non-inverting input of the amplifier (7) within the loop filter and having the electronic switch (17) control the loop filter bandwidth through changing the resistance (9, 11) to ground at the inverting input of the amplifier between a high and low value associated respectively with broad bandwidth and narrow bandwidth to the loop filter. Switching is possible in as little as one microsecond, and is accompanied by fast settling of the loop with minimal generation of phase/frequency perturbation. The foregoing PLL is of particular benefit in fast switching frequency synthesizers, such as used in frequency hopping frequency synthesizers of frequency and time division multiplexing systems.

摘要翻译： 通过将PLL的相位检测器（1）的相位误差信号馈送到相位检测器（1）的非反相输入端，在包含带宽切换有源环路滤波器（8）的锁相环（“PLL”）中实现快速切换和快速建立 环路滤波器内的放大器（7）并且具有电子开关（17），通过将放大器的反相输入端的电阻（9,11）改变为接地，控制环路滤波器带宽，分别与分别与宽 带宽和窄带宽到环路滤波器。 可以在短达1微秒的时间内进行切换，同时伴随着循环的快速建立，同时产生相位/频率扰动的最小化。 上述PLL在诸如频率和时分复用系统的跳频频率合成器中使用的快速开关频率合成器中特别有益。